Data output circuit with improved overvoltage/surge protection
View Patent ↗A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.
1. A data output circuit comprising:
first and second differential MOS transistors receiving first and second input voltages, respectively, sources of said differential MOS transistors being commonly connected;
first and second outputs;
a first cascade MOS transistor connected between said first differential MOS transistor and said first output;
a second cascade MOS transistor connected between said second differential MOS transistor and said second output, gates of said first and second cascade MOS transistors being commonly connected;
a first resistive element connected between a ground line and said commonly connected gates;
a second resistive element connected between a power supply line and said commonly connected gates;
a first MOS transistor connected between said first output and a gate of said first cascade MOS transistor, having a gate connected to said power supply line; and
a second MOS transistor connected between said second output and a drain and a gate of said second cascade MOS transistor, having a gate connected to said power supply line.
2. The data output circuit according to claim 1 , wherein said first resistive element comprises a P-channel MOS transistor having a gate clamped to a predetermined voltage level.
3. The data output circuit according to claim 1 , wherein said second resistive element comprises a P-channel MOS transistor having a gate clamped to a predetermined voltage level.
4. The data output circuit according to claim 1 , wherein said first MOS transistor comprises a first P-channel MOS transistor, and said second MOS transistor comprises a second P-channel MOS transistor.
5. The data output circuit according to claim 4 , further comprising:
a third P-channel MOS transistor having a source connected to said power supply line, and a substrate region short-circuited to a drain thereof,
wherein substrate regions of said first and second P-channel MOS transistors are connected to said substrate region of said third P-channel MOS transistor.
6. The data output circuit according to claim 5 , wherein said first resistive element comprises a fourth P-channel MOS transistor having a gate clamped to a predetermined voltage level and a substrate region connected to said substrate region of said third P-channel MOS transistor.
7. The data output circuit according to claim 5 , wherein said second resistive element comprises a fifth P-channel MOS transistor having a gate clamped to a predetermined voltage level and a substrate region connected to said substrate region of said third P-channel MOS transistor.
8. The data output circuit according to claim 5 , further comprising a third resistive element connected between said power supply line and said first and second output lines.
9. The data output circuit according to claim 8 , wherein said third resistive element comprises a sixth P-channel MOS transistor having a source connected to said power supply line, a drain connected to said first and second output lines, and a substrate region connected to said substrate region of said third P-channel MOS transistor.