IP Library Granted Patent US 7,394,275
Granted Patent B1
US 7,394,275 · App. 11/092,423 · Granted Jul 1, 2008

Systems and methods for generating and evaluating high frequency, low voltage swing signals at in-circuit testing

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Quick Facts
Patent No.
US 7,394,275
App. No.
11/092,423
Granted
Jul 1, 2008
Kind
B1
Abstract

Systems and methods for testing components of printed circuit assemblies (PCA) that generate high frequency, low voltage swing signals or that operate using such signals are disclosed. High frequency, low voltage swing signals from the PCA are divided and translated to low frequency signals exhibiting voltage swings compatible with an in-circuit test platform for evaluation. Additionally, high frequency signals exhibiting voltage swings compatible with a PCA are generated. The signals are sent to the PCA for testing components. The division/translation or signal generation/translation logic may be bypassed, enabling the in-circuit test platform and the PCA to send signals between each other even if power to the system is off.

Claims (20)

1. A system, comprising:

a translator for electrically connecting an in-circuit test platform with a printed circuit assembly, the translator translating a signal having a first voltage swing to a signal having a second voltage swing;

a bypass path for electrically connecting the in-circuit test platform with the printed circuit assembly; and

a switch for selectively transmitting a signal sent by the in-circuit test platform through either the translator or the bypass path.

2. The system of claim 1 , further comprising:

a clock source electrically connected to the translator that outputs a signal exhibiting the first voltage swing and having a high frequency.

3. The system of claim 2 , wherein the output signal of the clock source is input to the translator.

4. The system of claim 2 , wherein the clock source comprises a phase-locked loop.

5. The system of claim 2 , wherein the clock source has an input for receiving a signal from the in-circuit test platform.

6. The system of claim 1 , wherein the second voltage swing of the signal outputted from the translator is compatible with a component of the printed circuit assembly.

7. The system of claim 6 , wherein the second voltage swing comprises a low voltage swing.

8. The system of claim 1 , wherein the switch comprises a multiplexor.

9. The system of claim 1 , wherein the system is embodied as part of the in-circuit test platform.

10. The system of claim 1 , wherein the switch is controlled by the in-circuit test platform.

11. The system of claim 1 , wherein the printed circuit assembly and the in-circuit test platform communicate via the bypass path when power to the translator is off.

12. The system of claim 1 , wherein the bypass path facilitates testing for short or open circuits in the printed circuit assembly when power to the translator is off.

13. The system of claim 1 , wherein the system is an in-circuit testing system for testing a component of the printed circuit assembly for proper operation, wherein the component receives or generates signals having an oscillating signal.

14. The system of claim 1 , further comprising:

a bypass switch control; and

a header for providing an interface between the in-circuit test platform and the bypass switch control.

Assignments (13)
AMENDED AND RESTATED PATENT SECURITY AGREEMENT Recorded Jun 27, 2025
From: UNISYS CORPORATION; UNISYS HOLDING CORPORATION; UNISYS NPL, INC.; UNISYS AP INVESTMENT COMPANY I
To: COMPUTERSHARE TRUST COMPANY, N.A., AS COLLATERAL TRUSTEE
Reel/Frame 071759/0527 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2020
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: UNISYS CORPORATION
Reel/Frame 054231/0496 →
RELEASE OF SECURITY INTEREST Recorded Nov 9, 2017
From: WELLS FARGO BANK, NATIONAL ASSOCIATION (SUCCESSOR TO GENERAL ELECTRIC CAPITAL CORPORATION)
To: UNISYS CORPORATION
Reel/Frame 044416/0358 →
SECURITY INTEREST Recorded Oct 6, 2017
From: UNISYS CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 044144/0081 →
PATENT SECURITY AGREEMENT Recorded Apr 27, 2017
From: UNISYS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 042354/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
To: UNISYS CORPORATION
Reel/Frame 030082/0545 →
RELEASE OF SECURITY INTEREST Recorded Mar 15, 2013
From: DEUTSCHE BANK TRUST COMPANY
To: UNISYS CORPORATION
Reel/Frame 030004/0619 →
SECURITY AGREEMENT Recorded Jun 27, 2011
From: UNISYS CORPORATION
To: GENERAL ELECTRIC CAPITAL CORPORATION, AS AGENT
Reel/Frame 026509/0001 →
PATENT SECURITY AGREEMENT (JUNIOR LIEN) Recorded Oct 13, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023364/0098 →
PATENT SECURITY AGREEMENT (PRIORITY LIEN) Recorded Oct 12, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023355/0001 →
RELEASE BY SECURED PARTY Recorded Jul 31, 2009
From: CITIBANK, N.A.
To: UNISYS CORPORATION; UNISYS HOLDING CORPORATION
Reel/Frame 023086/0255 →
SECURITY AGREEMENT Recorded Jun 20, 2006
From: UNISYS CORPORATION; UNISYS HOLDING CORPORATION
To: CITIBANK, N.A.
Reel/Frame 018003/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2005
From: BARGER, WILLIAM J.; KELLEHER, THOMAS J.; CAPRIOTTI, MARK A.; JENNION, MARK W.
To: UNISYS CORPORATION
Reel/Frame 016326/0598 →