Power-consumption calculation method and apparatus
View Patent ↗An apparatus for calculating power consumption includes a behavioral synthesis unit for generating a clock-level description by behavioral synthesis of an algorithm description; a clock-level simulation unit for simulating a clock-level description and calculating operating ratios of storage elements and arithmetic units indicated by the clock-level description; a storage-element power calculation unit for calculating a predicted value of power consumption of a storage element portion based upon a power calculation formula, which has been read out of a power-calculation-formula file, and the operating ratios of the storage elements; and a combinational-circuit power calculation unit for calculating a predicted value of power consumption of an arithmetic unit portion based upon a power calculation formula, which has been read out of the power-calculation-formula file, and the operating ratios of the arithmetic units, and calculating a predicted value of power consumption of a combinational circuit, with the exception of arithmetic units, based upon a power calculation formula, which has been read out of the power-calculation-formula file, the operating ratios of the storage elements and arithmetic units and the operating ratios of input/output ports.
1. A power-consumption calculation method for calculating a predicted value of power consumption of a semiconductor device to be designed, comprising the steps of:
simulating a clock-level description in which operation of the semiconductor device to be designed is described as clock-level operation;
calculating operating ratios of storage elements and arithmetic units indicated by the clock-level description;
calculating a predicted value of power consumption of each storage element and each arithmetic unit based upon the calculated operating ratios of the storage elements and arithmetic units and power calculation formulae corresponding to respective ones of the storage elements and arithmetic units; and
calculating a predicted value of power consumption of a combinational circuit other than arithmetic units based upon the calculated operating ratios of the storage elements and arithmetic units and a power calculation formula prepared in conformity with the combinational circuit other than arithmetic units.
2. The method according to claim 1 , wherein said step of calculating a predicted value calculates the power consumption of each storage element on the assumption that a clock signal is input only when data is written to the storage element.
3. The method according to claim 1 , wherein if one or more of each of a storage element and arithmetic unit exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said step of calculating a predicted value of power consumption of a combinational circuit other than arithmetic units calculates a predicted value of power consumption of the combinational circuit other than arithmetic units using the operating ratios of the one or more storage elements and arithmetic units.
4. The method according to claim 1 , wherein if one or more storage elements exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said step of calculating a predicted value of power consumption of a combinational circuit other than arithmetic units calculates a predicted value of power consumption of the combinational circuit other than arithmetic units using the operating ratios of the one or more storage elements.
5. The method according to claim 1 , wherein if one or more arithmetic units exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said step of calculating a predicted value of power consumption of a combinational circuit other than arithmetic units calculates a predicted value of power consumption of the combinational circuit other than arithmetic units using the operating ratios of the one or more arithmetic units.
6. The method according to claim 1 , further comprising a step of assuming gate size based upon the clock-level description, and calculating a predicted value of leakage power based upon the gate size assumed.
7. A power-consumption calculation method for calculating a predicted value of power consumption of a semiconductor device to be designed, comprising the steps of:
simulating a clock-level description in which operation of the semiconductor device to be designed is described as clock-level operation,
calculating operating ratios of storage elements and arithmetic units indicated by the clock-level description;
calculating a predicted value of power consumption of each storage element and each arithmetic unit based upon the calculated operating ratios of the storage elements and arithmetic units and power calculation formulae corresponding to respective ones of the storage elements and arithmetic units;
assuming a virtual wiring area based upon the clock-level description and carrying out wiring of Clock-Tree-Synthesis CTS wiring in the virtual wiring area while calculating positions of buffers, which are inserted into the virtual wiring, based upon driving capability of the buffers and wiring capacitance of the virtual wiring; and
calculating a predicted value of power consumption by CTS based upon number of buffers that have been inserted into the virtual wiring at said step of wiring the CTS wiring.
8. A power-consumption calculation apparatus for simulating a clock-level description in which operation of a semiconductor device to be designed is described as clock-level operation and calculating a predicted value of power consumption of a semiconductor device to be designed, comprising:
storage-element power calculation means for calculating operating ratios of storage elements indicated by the clock-level description, and calculating a predicted value of power consumption of each storage element based upon the calculated operating ratios of the storage elements and a calculation formula for calculating power consumption of the storage elements;
combinational-circuit power calculation means for calculating operating ratios of arithmetic units indicated by the clock-level description, and
means for calculating a predicted value of power consumption of each arithmetic unit based upon the calculated operating ratios of the arithmetic units and a power calculation formula for calculating power consumption of the arithmetic units;
wherein said combinational-circuit power calculation means further calculates a predicted value of power consumption of the combinational circuit other than the arithmetic units based upon a power calculation formula for calculating power consumption of a combinational circuit other than the arithmetic units, the calculated operating ratios of the arithmetic units and operating ratios of the storage elements calculated by said storage-element power calculation means.
9. The apparatus according to claim 8 , wherein said storage-element power calculation means calculates a predicted value of power consumption of each storage element on the assumption that a clock signal is supplied only when data is written to the storage element.
10. The apparatus according to claim 8 , wherein if one or more of each of a storage element and arithmetic unit exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said combinational-circuit power calculation means calculates a predicted value of power consumption of the combinational circuit other than the arithmetic units using the operating ratios of the one or more storage elements and arithmetic units.
11. The apparatus according to claim 8 , wherein if one or more storage elements exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said combinational-circuit power calculation means calculates a predicted value of power consumption of the combinational circuit other than arithmetic units using the operating ratios of the one or more storage elements.
12. The apparatus according to claim 8 , wherein if one or more arithmetic units exist on a data path bracketing a combinational circuit other than arithmetic units to be calculated, said combinational-circuit power calculation means calculates a predicted value of power consumption of the combinational circuit other than arithmetic units using the operating ratios of the one or more arithmetic units.
13. The apparatus according to claim 8 , further comprising leakage-power calculation means for assuming gate size based upon the clock-level description and calculating a predicted value of leakage power based upon the gate size assumed.
14. A power-consumption calculation apparatus for simulating a clock-level description in which operation of a semiconductor device to be designed is described as clock-level operation and calculating a predicted value of power consumption of a semiconductor device to be designed, comprising:
storage-element power calculation means for calculating operating ratios of storage elements indicated by the clock-level description, and calculating a predicted value of power consumption of each storage element based upon the calculated operating ratios of the storage elements and a calculation formula for calculating power consumption of the storage elements;
combinational-circuit power calculation means for calculating operating ratios of arithmetic units indicated by the clock-level description, and
means for calculating a predicted value of power consumption of each arithmetic unit based upon the calculated operating ratios of the arithmetic units and a power calculation formula for calculating power consumption of the arithmetic units;
Clock-Tree-Synthesis CIS power calculation means for assuming a virtual wiring area based upon the clock-level description, carrying out wiring of CTS wiring in the virtual wiring area while calculating positions of buffers, which are inserted into the virtual wiring, based upon driving capability of the buffers and wiring capacitance of the virtual wiring; and
means for calculating a predicted value of power consumption by CTS based upon number of buffers that have been inserted into the virtual wiring.