High-speed serial transceiver with sub-nominal rate operating mode
View Patent ↗A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.
1. A communication device comprising:
a receiver operable with an unlocked sampling clock; and
a data recovery module configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data;
wherein the data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations attributable to the unlocked sampling clock; and
wherein the data recovery module further comprises:
a window register for storing a designated number of the data signal samples;
a plurality of phase edge counters receiving respective sets of samples from the window register, each counting edges for a designated bit position;
control circuitry coupled to the phase edge counters and identifying from their respective counts a particular phase; and
a data bit buffer for outputting one or more data bits responsive to the particular phase.
2. The communication device of claim 1 wherein the data recovery module further comprises:
a phase encoder for generating an output identifying the particular phase; and
a bit selector coupled between the window register and the data bit buffer, the bit selector receiving as a select signal the output of the phase encoder and supplying one or more of the data signal samples from the window register to the data bit buffer responsive to the select signal.
3. The communication device of claim 2 wherein the phase encoder stores phase information for a previous clock cycle and utilizes the stored phase information in conjunction with current phase information to detect an exception condition relating to the transition edge variations attributable to the unlocked sampling clock.
4. The communication device of claim 2 wherein the phase encoder is operative to detect an edge fallout condition and to cause at least one additional data signal sample to be supplied by the bit selector to the data bit buffer responsive to the detected edge fallout condition.
5. The communication device of claim 2 wherein the phase encoder is operative to detect an edge entry condition and to cause at least one less data signal sample to be supplied by the bit selector to the data bit buffer responsive to the detected edge entry condition.
6. The communication device of claim 2 wherein the data bit buffer stores one or more recovered data bits based at least in part on information about which of the bits are valid for a given clock cycle.
7. The communication device of claim 2 wherein rate mismatch causing one or more exception conditions is compensated by dropping one or more bits from or inserting one or more bits in a data stream of the data signal.
8. The communication device of claim 7 wherein the rate mismatch is compensated by shrinking or expanding an interpacket gap period of the data signal.
9. The communication device of claim 8 wherein the data bit buffer is operable in a packet mode and a compensation mode, the compensation mode performing the rate mismatch compensation and being initiated responsive to detection of the interpacket gap period in downstream circuitry of the communication device.
10. The communication device of claim 1 wherein the communication device is implemented as at least one integrated circuit.
11. The communication device of claim 1 , wherein the wherein the receiver is operable in at least first and second modes, the second mode having a data rate lower than that of the first mode, wherein the receiver in the first mode operates with a locked sampling clock, and in the second mode operates with the unlocked sampling clock.
12. The communication device of claim 11 wherein the locked sampling clock in the first mode is locked to a recovered transmit clock.
13. The communication device of claim 11 wherein the data rate of the second mode is below a lower bound of a nominal operating data rate range of the receiver.
14. The communication device of claim 11 wherein the data rate of the first mode is within a nominal operating data rate range of the receiver.
15. The communication device of claim 1 further comprising a serial transceiver, the serial transceiver comprising the receiver and a transmitter.
16. The communication device of claim 1 comprising reconfigurable hardware which implements at least a portion of the data recovery module.
17. The communication device of claim 16 wherein the reconfigurable hardware comprises at least one field programmable gate array.
18. The communication device of claim 11 wherein the first mode comprises a 100 Mb/s Ethernet mode and the second mode comprises a 1000 Mb/s Ethernet mode.
19. A method for use in a communication device comprising a receiver and a data recovery module, the method comprising the steps of:
operating the receiver with an unlocked sampling clock; and providing data signal samples, generated using the unlocked sampling clock, from the receiver to the data recovery module;
wherein the data recovery module is configured to detect transition edges in the data signal samples and to determine from the detected edges a sampling point for use in recovery of the associated data;
wherein the data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations attributable to the unlocked sampling clock; and
the method further comprises the steps of:
storing a designated number of the data signal samples in a window register;
counting edges for designated bit positions in respective ones of a plurality of phase edge counters receiving respective sets of samples from the window register;
identifying a particular phase from the respective counts of the phase edge counters; and
outputting one or more data bits from a data bit buffer responsive to the particular phase.
20. The method of claim 19 wherein the receiver is operable in at least first and second modes, the second mode having a data rate lower than that of the first mode, wherein the receiver in the first mode operates with a locked sampling clock, and in the second mode operates with the unlocked sampling clock.