Anti-fuse device
View Patent ↗An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
1. A device, comprising:
a source region laterally spaced from a drain region having a channel there between;
a gate oxide formed on said channel;
a gate formed on said gate oxide; and
lightly doped source and drain extension regions formed on both sides of said channel and extending across said channel from said source and said drain regions, respectively, occupying substantially all of said channel and forming an overlap region that occupies less than an entire length of said channel;
wherein said gate oxide is configured to break down in response to a programming current of about 5 mA; and
wherein device geometries correspond to a 0.13μ CMOS process.
2. The device as recited in claim 1 , wherein said source and drain regions are heavily doped with N-type material.
3. The device as recited in claim 1 , wherein said source and drain regions are heavily doped with P-type material.
4. The device according to claim 1 , further comprising:
a deep N-well region formed beneath said source region, said drain region, and said channel.
5. The device according to claim 4 , further comprising:
a lightly doped P-type substrate.
6. The device according to claim 1 , wherein said source region and said drain region are formed in an N-well.
7. The device according to claim 6 , further comprising:
a substrate;
wherein the source and drain regions, the source and drain extension regions, and the substrate are N-type.
8. The device as recited in claim 1 , wherein said overlap region has a different doping level than the source and drain extension regions.
9. The device as recited in claim 1 , wherein said gate oxide is configured to break-down across substantially all of said channel on application of power to said gate and one of said source region and said drain region.
10. The device of claim 1 , further comprising spacers abutting both sides of the gate and configured to be used in the formation of the source region and drain region.
11. The device of claim 10 , wherein the spacers are made of nitride or oxide.
12. The device according to claim 1 , further comprising:
a deep P-well region beneath the source region, the drain region, and the channel.
13. The device according to claim 1 , wherein the source region and the drain region are in a P-well.
14. The device according to claim 13 , further comprising:
a substrate;
wherein the source and drain regions, the source and drain extension regions, and the substrate are P-type.