Method of manufacturing a semiconductor device
View Patent ↗A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicide layer formation step). A direct nitride layer is formed on an entire region including the NiSi layer (a nitride layer formation step). Then an element that can increase heat-resisting temperature of the NiSi layer is implanted into the NiSi layer (an element implantation step). As a result, heat-resisting property of the NiSi layer can be increased, and thereby the NiSi layer can be inhibited from being transformed into a disilicide.
1. A method of manufacturing a semiconductor device provided with a MOS transistor, comprising:
a silicide layer formation step of forming an NiSi layer on at least one of a gate electrode and a source/drain region of said MOS transistor;
an element implantation step of implanting into said NiSi layer an inhibiter element which inhibits said NiSi layer from being transformed into a disilicide; and
a nitride layer formation step of forming an interlayer nitride film on said NiSi layer,
wherein said element implantation step includes implanting said element through said interlayer nitride film, such that said element reaches said NiSi layer.
2. The method according to claim 1 , said semiconductor device being provided with a P-MOS transistor and an N-MOS transistor, and said interlayer nitride film having a tensile stress,
wherein said element implantation step includes implanting said element only on said NiSi layer formed on said P-MOS transistor among those formed on said P-MOS transistor and said N-MOS transistor.
3. The method according to claim 1 , said semiconductor device being provided with a P-MOS transistor and an N-MOS transistor, and said interlayer nitride film having a compressive stress,
wherein said element implantation step includes implanting said element only on said NiSi layer formed on said N-MOS transistor among those formed on said P-MOS transistor and said N-MOS transistor.
4. The method according to claim 1 , wherein said inhibiter element implantation step includes implanting at least one element selected out of a group consisting of Ge, N, F, O and C.