Multi-threaded processor having compound instruction and operation formats

1. A multi-threaded processor comprising:

a memory;

an instruction decoder coupled to the memory for decoding instructions retrieved therefrom;

an integer unit coupled to the instruction decoder for processing integer type instructions received from the instruction decoder;

a vector unit coupled to the instruction decoder for processing vector type instructions received from the instruction decoder;

an accumulator unit associated with the vector unit for storing a first accumulator value; and

a reduction unit associated with the vector unit and the accumulator unit and configured to receive parallel data elements processed in the vector unit and to receive the first accumulator value from the accumulator unit, the reduction unit being operable to sum the parallel data elements and the first accumulator value, wherein the sum of the parallel data elements produces the same result as would be obtained if the parallel data elements were summed in series, and to generate a second accumulator value for delivery to the accumulator unit,

wherein one or more of the instructions are in a compound instruction format in which a single instruction comprises of multiple operation fields.

2. The multi-threaded processor of claim 1 , wherein one or more of the operation fields each comprising at least an operation code field and a function field, the operation code field and the function field together specifying a particular operation to be performed by one of the integer unit and the vector unit.

3. The multi-threaded processor of claim 2 , wherein the operation code and function fields have fixed size and locations within the operation fields.

4. The multi-threaded processor of claim 2 , wherein the operation codes comprise jump, constant, integer, load, store, copy to special register, copy from special register, and single instruction multiple data.

5. The multi-threaded processor of claim 1 , wherein a given one of the instructions in the compound instruction format comprises at least three operation fields.

6. The multi-threaded processor of claim 1 wherein a given one of the instructions in the compound instruction format comprises, in addition to the multiple operation fields, at least one additional field comprising dependency field.

7. The multi-threaded processor of claim 6 wherein the dependency field comprises a single bit field which indicates if compound operations designated in the multiple operation fields should be executed sequentially or in parallel.

8. The multi-threaded processor of claim 1 wherein a given one of the instructions in the compound instruction format comprises a 64-bit instruction having three 21-bit operation fields and a one-bit dependency field.

9. The multi-threaded processor of claim 1 wherein a given one of the instructions in the compound instruction format comprises a compound operation that is specified by two or more multiple operation fields of the instruction.

10. The multi-threaded processor of claim 1 wherein one or more of the operation fields of a given one of the instructions in the compound instruction format is restricted in terms of the particular operations which can be designated thereby.

11. The multi-threaded processor of claim 1 wherein one or more of the operation fields of a given one of the instructions in the compound instruction format is restricted to single instruction multiple data operations.

12. The multi-threaded processor of claim 1 wherein the processor comprises an integrated circuit.