Semiconductor device and a method of manufacturing the same
View Patent ↗Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p − type semiconductor region and p − type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n − type single crystal silicon layer 1 B is ρ (Ω·cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.148ρ.
1. A semiconductor device having a trench gate type MISFET formed on a semiconductor substrate, comprising:
a plurality of first trenches for the trench gate type MISFET, each extending a first direction on the semiconductor substrate;
a plurality of gate electrodes of the trench gate type MISFET formed in the first trenches;
a gate extraction electrode electrically connected with the plurality of gate electrodes of the trench gate type MISFET,
wherein a plurality of second trenches are formed between the gate extraction electrode and a source region of the trench gate type MISFET;
a plurality of conductive films are formed in the second trenches; and
the second trenches cross the first trenches.
2. A semiconductor device according to claim 1 , wherein the gate extraction electrode is disposed around the trench gate type MISFET.
3. A semiconductor device according to claim 1 , wherein the first and second trenches are formed in a same process; and
the gate electrode of the trench gate type MISFET and the conductive film in the second trenches are formed in a same process.
4. A semiconductor device having a MISFET comprising:
a semiconductor substrate having a main surface and a back surface;
a drain layer of the MISFET formed in the semiconductor substrate;
a channel layer of the MISFET formed over the drain layer;
a plurality of first trenches penetrating through the channel layer from the main surface of the semiconductor substrate;
a plurality of gate insulating films of the MISFET formed in the grooves;
a plurality of gate electrodes of the MISFET formed on the gate insulating films;
a plurality of source regions formed adjacent to the grooves; and
a gate extraction electrode electrically connected with the plurality of gate electrodes,
wherein the plurality of first trenches extend in a first direction on the main surface of the semiconductor substrate;
the gate extraction electrode is disposed round the MISFET on the main surface of the semiconductor substrate;
a plurality of second trenches crossing the first trenches are formed between the gate extraction electrode and the source region; and
a plurality of conductive films connecting the gate electrodes are formed in the second trenches.
5. A semiconductor device according to claim 5 , wherein the first and second trenches are formed in a same process; and
the gate electrode of the MISFET and the conductive film in the second trenches are formed in a same process.
6. A semiconductor device according to claim 4 , wherein the source region of the MISFET is not formed between the second trench and the gate extraction electrode.
7. A semiconductor device according to claim 4 , wherein each of the second trenches bridge between the adjacent first trenches.
8. A semiconductor device according to claim 4 , wherein the first trenches extend in parallel.
9. A semiconductor device according to claim 1 , wherein an insulating film is formed over the plurality of gate electrodes and gate extraction electrode:
a contact groove exposing the gate extraction electrode is formed in the insulating film; and
a gate line electrically connected with the gate extraction electrode is formed in the contact groove.
10. A semiconductor device according to claim 4 , wherein an insulating film is formed over the plurality of gate electrodes and gate extraction electrode;
a contact groove exposing the gate extraction electrode is formed in the insulating film; and
a gate line electrically connected with the gate extraction electrode is formed in the contact groove.
11. A semiconductor device according to claim 10 , wherein a source pad is formed over the insulating film; and the gate line and source pad are formed in a same process.