Hiding system latencies in a throughput networking system

1. A method for addressing system latency within a network system, comprising:

providing a network interface, the network interface including a plurality of direct memory access (DMA) channels, wherein each of the DMA channels is configured to transfer data between the network interface and a main system memory; and,

moving data within each of the plurality of direct memory access channels independently and in parallel to and from the main system memory so that one or more of the plurality of direct memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests, wherein the data is moved within each of the plurality of DMA channels independent and parallel with respect to each of the other ones of the plurality of DMA channels;

wherein the plurality of memory access channels include a plurality of receive memory access channels dedicated to moving data between the network interface and the memory system, wherein each of the plurality of receive memory access channels includes a receive descriptor ring.

2. The method of claim 1 wherein:

the network system allows relaxed ordering when internally moving data between the network interface and the memory system.

3. The method of claim 1 wherein:

one of the DMA channels includes dedicated queuing, control and buffering to move data while preserving ordering between a processing entity and the network interface.

4. The method of claim 3 wherein:

the data includes packets of information; and

multiple packets of information are sent at a time for a particular memory access channel.

5. The method of claim 2 further comprising:

selectively enforcing internal transaction ordering for some transactions within one of the DMA channels while keeping other transactions as relaxed ordering as necessary.

6. The method of claim 1 wherein:

each of the plurality of receive memory access channels includes a receive completion ring.

7. The method of claim 1 wherein:

the plurality of memory access channels include a plurality of transmit memory access channels dedicated to moving data between the memory system and the network interface.

8. The method of claim 7 wherein:

the plurality of transmit memory access channels include transmit descriptor rings.

9. A network system, comprising:

a plurality of processing entities;

a main system memory coupled to the plurality of processing entities;

a network interface coupled to the plurality of processing entities and the main system memory, the network interface including a plurality of direct memory access (DMA) channels, wherein each of the DMA channels is configured to transfer data between the network interface and a main system memory, wherein the network interface unit is configured to move data within each of the plurality of direct memory access channels independently and in parallel to and from main system memory so that one or more of the plurality of direct memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests, wherein the network interface unit is configured to move the data within each of the plurality of DMA channels independent and parallel with respect to each of the other ones of the plurality of DMA channels;

wherein the plurality of memory access channels include a plurality of receive memory access channels dedicated to moving data between the network interface and the memory system, wherein each of the plurality of receive memory access channels includes a receive descriptor ring.

10. The network system of claim 9 wherein:

the network system allows relaxed ordering when internally moving data between the network interface and the memory system.

11. The network system of claim 9 wherein:

one of the DMA channels includes dedicated queuing, control and buffering to move data while preserving ordering between a processing entity and the network interface.

12. The network system of claim 11 wherein:

the data includes packets of information; and

multiple packets of information are sent at a time for a particular memory access channel.

13. The network system of claim 10 , wherein the network interface is configured to:

selectively enforce internal transaction ordering for some transactions within one of the DMA channels while keeping other transactions as relaxed ordering as necessary.

14. The network system of claim 9 wherein:

each of the plurality of receive memory access channels includes a receive completion ring.

15. The network system of claim 9 wherein:

the plurality of memory access channels include a plurality of transmit memory access channels dedicated to moving data between the memory system and the network interface.

16. A network system, comprising:

a plurality of processing entities;

a main system memory coupled to the plurality of processing entities;

a network interface coupled to the plurality of processing entities and the main system memory, the network interface including a plurality of direct memory access (DMA) channels, wherein each of the DMA channels is configured to transfer data between the network interface and a main system memory, wherein the network interface unit is configured to move data within each of the plurality of direct memory access channels independently and in parallel to and from main system memory so that one or more of the plurality of direct memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests, wherein the network interface unit is configured to move the data within each of the plurality of DMA channels independent and parallel with respect to each of the other ones of the plurality of DMA channels;

wherein the plurality of memory access channels include a plurality of transmit memory access channels dedicated to moving data between the memory system and the network interface, wherein the plurality of transmit memory access channels include transmit descriptor rings.