Memory device capable of performing high speed reading while realizing redundancy replacement
View Patent ↗When normal bit lines BL 3 and /BL 3 are selected, spare bit lines SBL 2 and /SBL 2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals φ 1 and φ 2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals φ 1 and φ 2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.
1. A memory device comprising:
a plurality of memory cells storing information by a change in electric resistance value;
a read amplifying circuit performing parallel data reading on a plurality of selected memory cells selected simultaneously among said plurality of memory cells; and
a current path forming section forming a plurality of read current paths corresponding to said plurality of selected memory cells respectively between said read amplifying circuit and a supply source of a power supply potential, wherein
said plurality of read current paths are equal to each other substantially in physical length.
2. The memory device according to claim 1 , wherein
a part of said plurality of memory cells are spare memory cells each used instead of a defective memory cell when said defective memory cell exists in said plurality of normal memory cells, and
a part of said plurality of selected memory cells are said spare memory cells.
3. The memory device according to claim 1 , wherein each of said plurality of memory cells includes a magnetic storage element.
4. The memory device according to claim 1 , further comprising:
a dummy cell holding a reference value for discriminating data in said plurality of memory cells; and
a dummy bit line provided correspondingly to said dummy cell, wherein
said current path forming section forms reference current path corresponding to said dummy cell between said read amplifying circuit and said supply source of said power supply potential, and
said plurality of read current paths and said reference current path are equal to each other substantially in physical length.
5. A memory device comprising:
a memory cell array, said memory cell array including
a plurality of normal memory cells storing information by a change in electrical resistance value,
spare memory cells arranged in a matrix together with said plurality of normal memory cells, placed in a central portion in said memory cell array, and each used instead of a defective memory cell when said defective memory cell exists among said plurality of normal memory cells,
a plurality of bit lines placed along a column direction of said memory cell array, and for causing data read current to said plurality of normal memory cells,
a spare bit line placed along said column direction, and for causing a data read current into said spare memory cells,
a plurality of data lines transmitting a data read current flowing in a part of said plurality of bit lines and a data read current flowing in said spare bit line, and
a connecting gate circuit not only connecting a selected bit line among said plurality of bit lines to be selected according to a data read command to one of said plurality of data lines, but also connecting said spare bit line to another one of said plurality of data lines; and
a read amplifying circuit receiving a data read current transmitted by said plurality of data lines to read data in said plurality of normal memory cells and said spare memory cell.
6. A memory device comprising:
a memory cell array, said memory cell array including
a plurality of memory cells storing information by a change in electric resistance value,
a plurality of source lines provided on paths through which read currents for reading data from said plurality of memory cells,
dummy cells arranged in a matrix together with said plurality of memory cells, placed in a central portion of said memory cell array, and holding reference values for discriminating data in said plurality of memory cells,
dummy source lines provided on paths through which reference currents for reading said reference values from said dummy cells flow, and
a plurality of data lines transmitting said read currents and said reference currents; and
a read amplifying circuit receiving read currents and reference currents transmitted by said plurality of data lines to read data in said plurality of memory cells.