Integrated process for thin film resistors with silicides

1. A method of forming devices on a semiconductor wafer, the method comprising:

depositing an oxide layer overlaying the semiconductor wafer;

depositing a layer of SiCr;

depositing a mask layer of TiN overlaying the layer of SiCr;

patterning the layer of SiCr and TiN layer to a desired shape;

applying a HF/HCL cleaning process to the semiconductor wafer;

removing any remaining mask layer of TiN;

depositing one or more interconnect metal layers;

wherein applying a HF/HCL process further comprises, applying a 40:1 dilute of HF for approximately 60 seconds and applying a 6:1 dilute of HCL at approximately 50° C. for approximately 70 seconds.

2. The method of claim 1 , further comprising:

patterning a contact opening through the oxide layer to expose a portion of a working surface of the semiconductor wafer; and

depositing Pt to form a PtSi contact junction in the contact opening.

3. The method of claim 1 , further comprising:

patterning an opening through the one or more interconnect metal layers to the patterned layer of SiCr to form a thin film resistor.

4. The method of claim 1 , wherein patterning the layer of SiCr and TiN layer to a desired shape further comprises:

applying a TiN dry etch; and

applying a SiCr wet etch after the TiN dry etch.

5. The method of claim 1 , wherein patterning the layer of SiCr and TiN layer to a desired shape further comprises:

applying a TiN dry etch until the desired amount of TiN and SiCr layer is removed; and

applying at least one of a plasma and HF dip.

6. The method of claim 1 , further comprising:

forming at least one device junction in the semiconductor wafer.

7. The method of claim 6 , further comprising:

forming at least one field oxide layer on the working surface of the semiconductor wafer; and

using the at least one field oxide layer as a mask in defining an edge of the at least one device junction.

8. The method of claim 6 , further comprising:

forming a bottom plate of a capacitor with the at least one device junction;

forming an upper plate of the capacitor with the layer of SiCr and the one or more interconnect metal layers.

9. A method of forming a semiconductor device, the method comprising:

forming at least one hard mask overlaying at least one layer of resistive material;

forming at least one opening to a working surface of a silicon substrate of the semiconductor device;

cleaning the semiconductor device with a diluted HF/HCL process, wherein the diluted HF/HCL solution includes a 40:1 dilute of HF that is applied for approximately 60 seconds and a 6:1 HCL at approximately 50° C. that is applied for approximately 70 seconds;

after cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate; and

forming interconnect metal layers.

10. The method of claim 9 , further comprising:

forming at least one oxide layer between the working surface of the silicon substrate and the layer of resistive material.

11. The method of claim 9 , wherein the layer of resistive material is a SiCr layer.

12. The method of claim 9 , wherein the layer of resistive material is a NiCr layer.

13. The method of claim 9 , wherein the hard mask is a TiN layer.

14. The method of claim 9 , wherein the hard mask is a TiW layer.

15. The method of claim 9 , wherein forming the silicide contact junction further comprises:

depositing Pt in the opening to form a PtSi layer.

16. The method of claim 9 , further comprising:

removing the hard mask with peroxide after the formation of the at least one silicide contact junction.

17. The method of claim 9 , further comprising:

patterning the resistive material layer to form a resistor.

18. The method of claim 17 , wherein patterning the resistive material layer, further comprises:

applying a SiCr wet etch.

19. The method of claim 9 , further comprising:

patterning the interconnect metal layers.

20. The method of claim 19 , wherein patterning the interconnect metal layers, further comprises:

applying a dry etch to pattern a layer of AlCu of the interconnect metal layers; and

after the dry etch, applying a wet etch to pattern a layer of TiW of the interconnect metal layers.

21. A method of forming devices in an integrated circuit, the method comprising:

forming at least one patterned field oxide on a select portion of a working surface of a substrate of the integrated circuit;

forming at least one doped device junction in the substrate using the at least one field oxide as mask;

depositing an oxide layer overlaying the substrate;

depositing a SiCr layer overlaying the oxide layer;

depositing a mask TiN layer overlaying the SiCr layer;

patterning the TiN and SiCr layers;

forming at least one opening through the oxide layer to the at least one doped junction in the substrate;

cleaning the substrate with a diluted HF/HCL process;

after cleaning with the diluted HF/HCL process, forming at least one silicide contact junction in the at least one of the opening to the at least one doped junction;

removing any remaining mask TiN layer; and

forming interconnect metal layers.

22. The method of claim 21 , further comprising:

performing a aqua regia etch after forming the at least one silicide contact junction.