Method and system for packet synchronization
View Patent ↗A method and system for packet synchronization may comprise receiving a plurality of bits from an incoming sample of data. The received plurality of bits may be sliced at a first sampling rate. A logic level of at least one of the received plurality of bits may be determined based on the slicing of the received plurality of bits. The received plurality of bits may be synchronized with a channel access code based on determining the logic level of at least one of the received plurality of bits. The channel access code may be sampled at a higher frequency, to increase the probability of detecting whether the incoming bit is LOGIC 1 or LOGIC 0.
1. A method for signal processing, the method comprising:
receiving a plurality of bits for an incoming sample of data;
slicing said received plurality of bits at a first sampling rate;
determining a logic level of at least one of said received plurality of bits based on said slicing; and
synchronizing said received plurality of bits with a channel access code based on said determined logic level.
2. The method according to claim 1 , comprising modifying said first sampling rate of said slicing to increase a likelihood of detecting an error in said received plurality of bits.
3. The method according to claim 2 , comprising dynamically modifying said first sampling rate of said slicing.
4. The method according to claim 1 , comprising increasing said first sampling rate of said slicing to increase said likelihood of detecting said error in said received plurality of bits.
5. The method according to claim 4 , comprising dynamically increasing said first sampling rate of said slicing.
6. The method according to claim 1 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a positive frequency deviation.
7. The method according to claim 1 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a positive frequency deviation.
8. The method according to claim 1 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a negative frequency deviation.
9. The method according to claim 1 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a negative frequency deviation.
10. The method according to claim 1 , comprising generating a synchronized output packet based on said determined logic level of a received bit based on said slicing and said received plurality of bits for said incoming sample of data.
11. A machine-readable storage having stored thereon, a computer program having at least one code section for signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
receiving a plurality of bits for an incoming sample of data;
slicing said received plurality of bits at a first sampling rate;
determining a logic level of at least one of said received plurality of bits based on said slicing; and
synchronizing said received plurality of bits with a channel access code based on said determined logic level.
12. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for modifying said first sampling rate of said slicing to increase a likelihood of detecting an error in said received plurality of bits.
13. The machine-readable storage according to claim 12 , wherein said at least one code section comprises code for dynamically modifying said first sampling rate of said slicing is done dynamically.
14. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for increasing said first sampling rate of said slicing to increase said likelihood of detecting said error in said received plurality of bits.
15. The machine-readable storage according to claim 14 , wherein said at least one code section comprises code for dynamically increasing said first sampling rate of said slicing.
16. The machine-readable storage according to claim 11 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a positive frequency deviation.
17. The machine-readable storage according to claim 11 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a positive frequency deviation.
18. The machine-readable storage according to claim 11 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a negative frequency deviation.
19. The machine-readable storage according to claim 11 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a negative frequency deviation.
20. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for generating a synchronized output packet based on said determined logic level of a received bit based on said slicing and said received plurality of bits for said incoming sample of data.
21. A system for signal processing, the system comprising:
one or more circuits that are operable to receive a plurality of bits for an incoming sample of data;
said one or more circuits are operable to slice said received plurality of bits at a first sampling rate;
said one or more circuits are operable to determine a logic level of at least one of said received plurality of bits based on said slicing; and
said one or more circuits are operable to synchronize said received plurality of bits with a channel access code based on said determined logic level.
22. The system according to claim 21 , wherein said one or more circuits are operable to modify said first sampling rate of said slicing to increase a likelihood of detecting an error in said received plurality of bits.
23. The system according to claim 22 , wherein said one or more circuits are operable to dynamically modify said first sampling rate of said slicing.
24. The system according to claim 21 , wherein said one or more circuits are operable to increment said first sampling rate of said slicing to increase said likelihood of detecting said error in said received plurality of bits.
25. The system according to claim 24 , wherein said one or more circuits are operable to dynamically increment said first sampling rate of said slicing.
26. The system according to claim 21 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a positive frequency deviation.
27. The system according to claim 21 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a positive frequency deviation.
28. The system according to claim 21 , wherein said determined logic level of a received bit is LOGIC 1, when said received bit has a negative frequency deviation.
29. The system according to claim 21 , wherein said determined logic level of a received bit is LOGIC 0, when said received bit has a negative frequency deviation.
30. The system according to claim 21 , wherein said one or more circuits are operable to generate a synchronized output packet based on said determined logic level of a received bit based on said slicing and said received plurality of bits for said incoming sample of data.