Mechanism for lossless user-level tracing on an architecture supporting PC-relative addressing

1. A method for tracing an instrumented program comprising:

triggering a probe in the instrumented program;

obtaining an original instruction associated with the probe;

copying a program counter value into a register not used by the original instruction if the original instruction is a position-dependent instruction but not a control-flow instruction, the original instruction dependent on a program counter comprising the program counter value;

obtaining a modified instruction by modifying the original instruction to be dependent on the register holding a copy of the program counter value;

storing the modified instruction into a scratch space;

storing a move instruction for an architecture that supports program counter (pc)-relative addressing into the scratch space, wherein the move instruction comprises data for restoring an original value of the register holding the copy of the program counter value;

storing a jump instruction for the architecture that supports pc-relative addressing into the scratch space, wherein the jump instruction includes a next program counter value;

executing the modified instruction in the scratch space using the thread;

executing the move instruction in the scratch space using the thread to restore the original value of the register; and

executing the jump instruction in the scratch space using the thread.

2. The method of claim 1 , further comprising:

if the original instruction is the control-flow instruction:

emulating the original instruction to determine the next program counter value; and

returning control to the thread at an address of the next program counter value.

3. The method of claim 1 , further comprising:

determining the next program counter value by incrementing a value of the program counter using a size of the original instruction.

4. The method of claim 1 , wherein the probe corresponds to a trap.

5. The method of claim 1 , wherein obtaining the original instruction comprises:

searching a look-up table using the program counter value, wherein the look-up table comprises the original instruction associated with the probe and an address associated with the original instruction.

6. The method of claim 1 , wherein the scratch space is allocated on a per-thread basis.

7. The method of claim 1 , wherein the instrumented program is executed on a multi-thread architecture.

8. A system for tracing an instrumented program comprising:

a processor that supports program counter (pc)-relative addressing, the processor for executing a thread configured to execute the instrumented program;

a memory configured to store a look-up table arranged to store an address and a corresponding original instruction;

a trap handler configured to;

halt execution of the thread when a trap instruction is encountered,

use an address of the trap instruction to obtain the corresponding original instruction from the look-up table,

move a copy of a program counter to a register not used by the original instruction if the original instruction is a position-dependent instruction but not a control-flow instruction, the original instruction dependent on the program counter comprising a program counter value,

obtain a modified instruction by modifying the original instruction to be dependent on the register holding the copy of the program counter value,

generate a jump instruction for an architecture that supports pc-relative addressing to an address in the instrumented program, and

generate a move instruction for an architecture that supports pc-relative addressing, wherein the move instruction comprises data for restoring the register holding the copy of the program counter value;

a scratch space arranged to store the modified instruction, the move instruction, and the jump instruction; and

an execution facility for:

executing the original modified instruction to collect data,

executing the move instruction to restore the register holding the copy of the program counter value, and

executing the jump instruction, wherein the execution facility is the processor supporting pc-relative addressing.

9. The system of claim 8 , further comprising:

a buffer for storing data.

10. The system of claim 8 , further comprising:

a tracing framework configured to emulate the original instruction to determine a value of the program counter if the original instruction is the control-flow instruction and to return control to the thread at an address of the program counter value if the original instruction is the control-flow instruction.

11. The system to claim 8 , wherein the trap handler sets a destination of the jump instruction to a next address immediately following an address of the trap instruction.

12. The system of claim 8 , wherein the scratch space is allocated on a per-thread basis.

13. The system of claim 8 , wherein the instrumented program is executed on a multi-thread architecture.