Method and system for frequency feedback adjustment in digital receivers
View Patent ↗In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by utilizing the Forward Error Correction (FEC) repetition rate in a header of a Bluetooth packet. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.
1. A method for signal processing, the method comprising:
monitoring a transmitter frequency during a channel access code portion of a Bluetooth packet;
determining a DC offset estimate between said transmitter frequency and a receiver frequency; and
adjusting said receiver frequency during a header portion of said Bluetooth packet based on said determined DC offset estimate when said determined DC offset estimate is outside a range of a threshold value.
2. The method according to claim 1 , comprising dynamically modifying said range of said threshold value.
3. The method according to claim 1 , wherein said range of said threshold value is symmetrical.
4. The method according to claim 1 , comprising dynamically adjusting said receiver frequency.
5. The method according to claim 1 , comprising generating a frequency adjustment signal for decreasing said receiver frequency.
6. The method according to claim 1 , comprising generating a frequency adjustment signal for increasing said receiver frequency.
7. The method according to claim 1 , comprising modifying at least one register bit to decrease said receiver frequency.
8. The method according to claim 1 , comprising modifying at least one register bit to increase said receiver frequency.
9. The method according to claim 1 , comprising generating a counter value for adjusting said receiver frequency.
10. The method according to claim 1 , comprising determining said DC offset estimate via DC offset slicing.
11. A system for signal processing, the system comprising:
a modem that monitors a transmitter frequency during a channel access code portion of a Bluetooth packet;
said modem determines a DC offset estimate between said transmitter frequency and a receiver frequency; and
said modem adjusts said receiver frequency during a header portion of said Bluetooth packet based on said determined DC offset estimate when said determined DC offset estimate is outside a range of a threshold value.
12. The system according to claim 11 , wherein said modem dynamically modifies said range of said threshold value.
13. The system according to claim 11 , wherein said range of said threshold value is symmetrical.
14. The system according to claim 11 , wherein said modem dynamically adjusts said receiver frequency.
15. The system according to claim 11 , wherein said modem generates a frequency adjustment signal for decreasing said receiver frequency.
16. The system according to claim 11 , wherein said modem generates a frequency adjustment signal for increasing said receiver frequency.
17. The system according to claim 11 , wherein said modem modifies at least one register bit to decrease said receiver frequency.
18. The system according to claim 11 , wherein said modem modifies at least one register bit to increase said receiver frequency.
19. The system according to claim 11 , wherein said modem generates a counter value for adjusting said receiver frequency.
20. The system according to claim 11 , wherein said modem determines said DC offset estimate via DC offset slicing.