Storage element for mitigating soft errors in logic
View Patent ↗In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed clock signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
1. A method for reducing soft errors in logic comprising:
obtaining a first delayed clock signal;
obtaining a second delayed clock signal;
applying a clock signal, the first delayed clock signal, the second delayed clock signal and a data output from a logic circuit to a triple redundant memory element;
wherein the time delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
wherein the time delay of the second delayed clock is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit;
wherein an original logic value on the data output from the logic circuit before a soft error occurs is maintained on an output of the triple redundant memory element after the soft error occurs;
wherein the triple redundant memory element comprises:
three memory elements;
a majority voting logic circuit;
wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
wherein the clock signal is connected to a first memory element;
wherein the first delayed clock signal is connected to a second memory element;
wherein the second delayed clock signal is connected to a third memory element.
2. The method as in claim 1 wherein the memory elements are DRAMS.
3. The method as in claim 1 wherein the memory elements are SRAMs.
4. The method as in claim 1 wherein the memory elements are D-type flip-flops.
5. The method as in claim 1 wherein the memory elements are pulsed latches.
6. The method as in claim 1 wherein the majority voting logic circuit comprises:
three two-input NANDs;
one three-input NAND;
wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
7. The method as in claim 1 wherein the majority voting logic circuit comprises:
three two-input ANDs;
one three-input OR;
wherein each output from the three two-input ANDs are connected to an input of the three-input OR.
8. A circuit for reducing soft errors in logic comprising:
a first delay element;
a second delay element;
a triple redundant memory element;
wherein a clock signal is applied to the first delay element, the second delay element, and to a triple redundant memory element;
wherein an output of a logic circuit is applied to the triple redundant memory element;
wherein the time delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
wherein the time delay of the second delayed clock is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit;
wherein an original logic value on the data output from the logic circuit before a soft error occurs is maintained on an output of the triple redundant memory element the soft error occurs;
wherein the triple redundant memory element comprises:
three memory elements;
a majority voting logic circuit;
wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
wherein the clock signal is connected to a first memory element;
wherein the first delayed clock signal is connected to a second memory element;
wherein the second delayed clock signal is connected to a third memory element.
9. The circuit as in claim 8 wherein the memory elements are DRAMS.
10. The circuit as in claim 8 wherein the memory elements are SRAMs.
11. The circuit as in claim 8 wherein the memory elements are D-type flip-flops.
12. The circuit as in claim 8 wherein the memory elements are pulsed latches.
13. The circuit as in claim 8 wherein the majority voting logic circuit comprises:
three two-input NANDs;
one three-input NAND;
wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
14. The circuit as in claim 8 wherein the majority voting logic circuit comprises:
three two-input ANDs;
one three-input OR;
wherein each output from the three two-input ANDs are connected to an input of the three-input OR.