High-performance charge-pump circuit for phase-locked loops
View Patent ↗One of the high-performance charge-pump circuits basically includes two switch mirror circuits, two current sources, two switches, and an inverter. In the switch mirror, the switch coupled to the diode-connected reference transistor is indirectly mirrored to the output. The great advantage is to utilize the switch mirrors as a part of building cascodes at the output. Consequently, all high-performance charge-pump circuits suppress any charge-injection errors, reduce charge-pump offset, increase the output impedance for effective current injection, and reduce chare-sharing problem.
1. A high-performance charge-pump circuit for receiving phase detector outputs and generating an average current flowing into or flow out of the charge-pump circuit output node, comprising:
a first current mirror circuit consisting of two diode-connected transistors on its input side, and two transistors for a first output current source and a current source transistor coupled to the charge-pump circuit output node for a second output current source, wherein the input side receives a reference current which is relatively independent of temperature, supply, and process variations and the two output sides provide the reference current;
a second current mirror circuit consisting of a diode-connected transistor and a transistor on its input side, and a current source transistor coupled to the charge-pump circuit output node, wherein the input side of the second current mirror circuit is coupled to receive the reference current from the first output current source of the first current mirror circuit and the output side of the second current mirror circuit provides the reference current;
a PMOS switch mirror circuit having a diode-connected reference transistor and a output transistor coupled to receive a switching signal and send the switching signal to the current source transistor of the second current mirror circuit;
a NMOS switch mirror circuit having a diode-connected reference transistor and a output transistor coupled to receive a switching signal and send the switching signal to the second output current source transistor of the first current mirror circuit; and
two switches for receiving the up and down signals from the phase detector, wherein each switch is coupled between a rail and a reference transistor of a switch mirror circuit.
2. The circuit as recited in claim 1 wherein the switch consists of a PMOS transistor and a NMOS transistor.
3. The circuit as recited in claim 1 wherein the switch is a CMOS transistor.
4. The circuit as recited in claim 1 wherein the gate terminal of the PMOS switch transistor is coupled to an odd number of inverter gates.
5. The circuit as recited in claim 1 wherein the phase detector is phase detector.
6. The circuit as recited in claim 1 wherein the phase detector is phase-frequency detector.
7. The circuit as recited in claim 1 wherein the switch mirror circuit includes a diode-connected reference transistor, whose drain terminal is connected to the drain terminal of a switch.
8. The circuit as recited in claim 7 wherein the switch mirror circuit mirrors the switching action to the drain of the output transistor.
9. The circuit as recited in claim 1 wherein the rail coupled to the NMOS transistor being used as a switch is ground.
10. The circuit as recited in claim 1 wherein the rail coupled to the PMOS transistor being used as a switch is power supply.
11. The circuit as recited in claim 1 wherein the high-performance charge-pump circuit is applied to all phase-locked loops without regard to architectures, topologies, and schematics.
12. A high-performance charge-pump circuit for receiving phase detector outputs and generating an average current flowing into or flow out of the charge-pump circuit output node, comprising:
two switched current mirror circuits consisting of a diode-connected transistor and a transistor on its input side, and a current source transistor and a switch on its output side, wherein each switched current mirror circuit is coupled to receive a reference current which is relatively independent of temperature, supply, and process variations and send the switched reference current;
two switches for receiving the up and down signals from the phase detector, wherein each switch is coupled between a rail and a current source transistor of a switched current mirror circuit; and
two current mirror circuits for receiving the switched reference current and sending the switched reference current to the charge-pump circuit output node, wherein each current mirror circuit is coupled between a switched current mirror circuit and the charge-pump circuit output node.
13. The circuit as recited in claim 12 wherein the switch consists of a PMOS transistor and a NMOS transistor.
14. The circuit as recited in claim 12 wherein the switch is a CMOS transistor.
15. The circuit as recited in claim 12 wherein the gate terminal of the PMOS switch transistor is coupled to an odd number of inverter gates.
16. The circuit as recited in claim 12 wherein the current mirror circuits are cascode current mirror circuits.
17. The circuit as recited in claim 12 wherein the current mirror circuits are Wilson current mirror circuits.
18. The circuit as recited in claim 12 wherein the rail coupled to the NMOS transistor being used as a switch is ground.
19. The circuit as recited in claim 12 wherein the rail coupled to the PMOS transistor being used as a switch is power supply.
20. The circuit as recited in claim 12 wherein the high-performance charge-pump circuit is applied to all phase-locked loops without regard to architectures, topologies, and schematics.