Successive approximation analog-to-digital converter with current steered digital-to-analog converter
View Patent ↗A successive approximation Analog-to-Digital Converter (“ADC”) having a successive approximation controller operably coupled to convert a control signal into a digital output of the successive approximation ADC, a current-steered Digital-to-Analog Converter operably coupled to convert the digital output of the successive approximation ADC into an analog feedback signal, and a comparator module operably coupled to compare the analog feedback signal with an analog input of the successive approximation ADC to produce the control signal. A further aspect is a method for increasing accuracy for a digital successive approximation of an analog input signal. The method includes determining a signal characteristic of the analog input signal to an Analog-to-Digital Converter (“ADC”), and selecting a reference voltage source of a Digital-to-Analog Converter of the ADC from a plurality of reference voltage sources based on the analog input signal.
1. A successive approximation Analog-to-Digital Converter (“ADC”) comprises:
a successive approximation controller (“SAC”) operably coupled to convert a control signal into a digital output of the successive approximation ADC;
a current-steered Digital-to-Analog Converter (“DAC”) operably coupled to convert the digital output of the successive approximation ADC into an analog feedback signal, wherein the current-steered DAC includes a voltage reference selector operable to produce a plurality of voltage reference values, wherein the reference voltage is selected from the plurality of voltage reference values and is based on the analog input of the successive approximation ADC; and
a comparator module operably coupled to compare the analog feedback signal with an analog input of the successive approximation ADC to produce the control signal.
2. The successive approximation ADC of claim 1 , wherein the comparator module comprises:
a comparator having a first input, a second input, and an output, wherein the second input of the comparator is operably coupled to receive the analog feedback signal; and
a sample-and-hold circuit having an input and an output, the sample-and-hold circuit input operably coupled to generate a selectively sampled-and-held representation of an analog signal, and the sample-and-hold circuit output operably coupled to provide the analog input of the successive approximation ADC to the first input of the comparator.
3. The successive approximation ADC of claim 1 , wherein the SAC comprises:
a successive approximation logic, and
a register operably coupled to the successive approximation logic, in which the successive approximation logic manipulates a register content of the register according to the control signal.
4. The successive approximation ADC of claim 3 , wherein the current-steered digital-to-analog converter comprises:
a plurality of controllable current sources each being controllable between a first state and a second state; and
a control logic module coupled to the controllable current sources and configured to (i) control digital to analog conversion based on a sampling interval and (ii) control each of the controllable current sources to switch between the first state and the second state with respect to the sampling interval.
5. The successive approximation ADC of claim 1 wherein:
the first and the second inputs of the comparator are differential inputs.
6. The successive approximation ADC of claim 1 wherein:
the current-steered DAC comprises at least one of a thermometer-weighted topology and a binary-weighted topology.
7. A successive approximation Analog-to-Digital Converter (“ADC”) comprising:
a current-steered Digital-to-Analog Converter (“DAC”) operable to convert a digital output of the successive approximation ADC into an analog feedback signal, wherein the current-steered DAC includes a voltage reference selector operable to produce a plurality of voltage reference values, wherein the reference voltage is selected from the plurality of voltage reference values and is based on the analog input of the successive approximation ADC; and
a successive approximation controller (“SAC”) operably coupled to produce the digital output of the successive approximation ADC based on a comparison result signal, wherein the comparison result signal indicates a successive relative position of the analog feedback signal with respect to an analog input voltage of the successive approximation ADC such that the digital output corresponds to the analog input voltage.
8. The successive approximation ADC of claim 7 wherein:
the analog output of the current-steered DAC and the analog input voltage of the successive approximation ADC are each of a differential signal format.
9. The successive approximation ADC of claim 7 wherein the current-steered DAC comprises:
at least one of a thermometer-weighted topology and a binary-weighted topology.
10. The successive approximation ADC of claim 7 further comprises:
a sample-and-hold circuit having an input and an output, the input operably coupled to generate a selectively sampled-and-held representation of an analog signal, and the output operably coupled to provide the analog input voltage of the successive approximation ADC for comparison to the analog output of the current-steered DAC.
11. The successive approximation ADC of claim 10 wherein:
the analog output of the current-steered DAC and the analog input voltage of the successive approximation ADC are each of a differential signal format.
12. The successive approximation ADC of claim 11 wherein:
the current-steered DAC comprises at least one of a thermometer-weighted topology and a binary-weighted topology.
13. The successive approximation ADC of claim 7 further comprises:
a sample-and-hold module operably coupled to provide the analog input voltage for comparison to the analog output of the current-steered DAC.
14. The successive approximation ADC of claim 13 wherein the current-steered DAC comprises:
at least one of a thermometer-weighted topology and a binary-weighted topology.