Memory interface for volatile and non-volatile memory devices
View Patent ↗Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.
1. A method, comprising:
providing access to and from different volatile and non-volatile memory devices with different kinds of capabilities through a common interface, by
addressing data on a connected volatile or non-volatile memory device, and controlling at least data flow to and from the connected memory device through said common interface, and
transferring data to and from the connected volatile or non-volatile memory device through at least one data bus of said common interface,
wherein commands on the common interface are adjusted depending on the volatile or non-volatile memory device connected to said common interface, and
wherein a latency set range of said volatile or non-volatile memory device is requested from the connected volatile or nonvolatile memory device through said common interface,
wherein a latency timing is then set by changing a latency register setting to a value in said latency set range,
such that said different types of volatile or non-volatile memory devices with different kinds of data capabilities are usable with said common interface.
2. The method of claim 1 , further comprising setting at least a first latency depending on the memory device connected to the common interface using commands on the command bus to the connected memory device.
3. The method of claim 2 , wherein the first latency is set by changing a latency register setting within the memory device.
4. The method of claim 2 , wherein the commands for adjusting the first latency are reserved for a different use with other memory devices.
5. The method of claim 2 , wherein the first latency is set during configuring the common interface for accessing the connected volatile or non-volatile memory device.
6. The method of claim 1 , further comprising setting at least a burst mode latency depending on the type of memory device connected to the common interface using commands on the command bus.
7. The method of claim 1 , further comprising selecting the volatile or non-volatile memory device supported by the interface using a chip select signal.
8. The method of claim 1 , wherein adjusting the first latency depends on the type of memory device being one of
A) a volatile memory device;
B) a non-volatile memory device.
9. Apparatus, comprising:
a common interface for interfacing between an integrated circuit and any connected one of a plurality of different volatile and non-volatile memory devices with different kinds of capabilities, said common interface for addressing data, and for controlling at least data flow to and from the connected memory device selected from said different volatile and non-volatile memory devices, comprising:
a data bus for transferring data to and from the connected volatile or non volatile memory device, and
the common interface is arranged to adjust commands depending on the volatile or non-volatile memory device connected to the common interface and to request a latency set range of said connected memory device from the connected memory device in order to change a latency register setting, such that said different memory devices with different kinds of capabilities are connectable to said common interface enabling use of said any connected one of said plurality of different volatile and non-volatile memory devices with said common interface.
10. Integrated circuit comprising an apparatus of claim 9 .
11. A computer-system comprising a central processing unit and a memory device, where the central processing unit is in connection with the memory device via an apparatus of claim 9 .
12. The computer system of claim 11 , wherein plural memory devices are in connection with the processing unit.
13. The computer system of claim 11 , wherein the processing unit is arranged for selecting the type of memory device connected to the interface.
14. A computer program product with a computer program stored thereon, the program comprising instructions operating at least one processor to transfer data between a memory device selected from different volatile and non-volatile memory devices with different kinds of capabilities and an integrated circuit over a common interface used regardless of the volatile and non-volatile memory device selected such that commands on said common interface are adjustable depending on the volatile and non-volatile memory device connected to the common interface, wherein a latency set range of said connected memory device is requested from the memory device through said common interface to enable a change in a latency register setting, such that said different volatile and non-volatile memory devices with different kinds of capabilities are usable with said common interface.
15. A device comprising:
a central processing unit and a connected memory device selected from different volatile and non-volatile memory devices, said device further comprising a common interface for interfacing between the central processing unit and any volatile and non-volatile memory device selected from among said different volatile and non-volatile memory devices, the common interface for addressing data, and for controlling at least data flow to and from the connected volatile and non-volatile memory device selected from said different volatile and non-volatile memory devices, comprising:
a data bus for transferring data to and from the connected volatile and non-volatile memory device, and
the common interface is arranged to adjust commands depending on the memory device connected to the common interface and to request a latency set range of said memory device from the memory device through said common interface to enable a change in a latency register setting, such that said different volatile and non-volatile memory devices with different kinds of capabilities are connectable to said common interface enabling use of said different volatile and non-volatile memory devices with said common interface.
16. The device of claim 15 , where the device is a mobile communication device.