Transistors and methods of manufacture thereof
View Patent ↗Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate includes and include respectively a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage V t of the transistor. The transistor may includes and include respectively a single NMOS transistor or an NMOS transistor of a CMOS device.
1. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming a gate dielectric material over the workpiece;
exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si) to form a gate material over the gate dielectric material, the gate material comprising a layer of a combination of Hf and Si;
patterning the gate material and the gate dielectric material to form a gate and a gate dielectric of a transistor, respectively, wherein the gate comprises a first thickness and wherein the ratio of Hf to Si is substantially the same throughout the first thickness of the gate; and
forming a source region and a drain region in the workpiece proximate the gate dielectric.
2. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming a gate dielectric material over the workpiece;
exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si) to form a gate material over the gate dielectric material, the gate material comprising a layer of a combination of Hf and Si, wherein exposing the workpiece to the precursor of Hf comprises exposing the workpiece to TDEAH, Hf(NEt 2 ) 4 , or TEMAH;
patterning the gate material and the gate dielectric material to form a gate and a gate dielectric of a transistor, respectively; and
forming a source region and a drain region in the workpiece proximate the gate dielectric.
3. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming a gate dielectric material over the workpiece;
exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si) to form a gate material over the gate dielectric material, the gate material comprising a layer of a combination of Hf and Si, wherein exposing the workpiece to the precursor of Si comprises exposing the workpiece to TDMAS, Tetrakis (dimethylamido), [(CH 2 ) 2 N] 4 Si, or SiH 4 ;
patterning the gate material and the gate dielectric material to form a gate and a gate dielectric of a transistor, respectively; and
forming a source region and a drain region in the workpiece proximate the gate dielectric.
4. The method according to claim 1 , wherein forming the gate dielectric comprises forming a hafnium-based dielectric, HfO 2 , HfSiO X , Al 2 O 3 , ZrO 2 , ZrSiO X , Ta 2 O 5 , La 2 O 3 , nitrides thereof, Si x N y , SiON, HfAlO x , HfAlO x N 1-x-y , ZrAlO x , ZrAlO x N y , SiAlO x , SiAlO x N 1-x-y , HfSiAlO x , HfSiAlO x N y , ZrSiAlO x , ZrSiAlO x N y , SiO 2 , combinations thereof, or multiple layers thereof.
5. The method according to claim 1 , further comprising a post deposition anneal (PDA) process.
6. The method according to claim 5 , wherein the post deposition anneal process comprises a temperature of about 700 degrees C. in an ambient of NH 3 .
7. The method according to claim 1 , wherein forming the gate material further comprises forming a layer of semiconductive material over the layer of the combination of Hf and Si.
8. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming a gate dielectric material over the workpiece;
exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si) to form a gate material over the gate dielectric material, the gate material comprising a layer of a combination of Hf and Si, wherein exposing the workpiece to the precursor of Hf and the precursor of Si further comprises forming a gate comprised of about 10% or less of oxygen (O), carbon (C), nitrogen (N), or combinations thereof;
patterning the gate material and the gate dielectric material to form a gate and a gate dielectric of a transistor, respectively; and
forming a source region and a drain region in the workpiece proximate the gate dielectric.
9. The method according to claim 1 , exposing the workpiece to the precursor of Hf and the precursor of Si comprises forming a first gate of a negative channel metal oxide semiconductor (NMOS) transistor, further comprising forming a second gate comprising a different material than the material of the first gate, the second gate comprising a gate of a positive channel metal oxide semiconductor (PMOS) transistor.