Large-area nanoenabled macroelectronic substrates and uses therefor
View Patent ↗A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
1. A device comprising:
a substrate;
a thin film consisting of a plurality of nanowires or a plurality of nanowires in solution-on the substrate, wherein each of said plurality of nanowires have a same conductive property as each of the other nanowires in said thin film;
a first source contact and a first drain contact formed in or on the substrate, wherein at least two or more of the plurality of nanowires form a channel between said first source and drain contacts; and
a first gate contact formed on, above or below said at least two or more nanowires.
2. The device of claim 1 , wherein at least five or more nanowires form a channel between said first source and drain contacts.
3. The device of claim 1 , wherein at least ten or more nanowires form a channel between said first source and drain contacts.
4. The device of claim 1 , whereinat least 100 or more nanowires form a channel between said first source and drain contacts.
5. The device of claim 1 , wherein the plurality of nanowires comprises nanowires selected from Group II–VI semiconductors, Group III–V semiconductors and Group IV semiconductors.
6. The device of claim 1 , wherein the plurality of nanowires comprises a plurality of nanoribbons.
7. The device of claim 1 , wherein the plurality of nanowires are aligned substantially parallel to their long axis.
8. The device of claim 1 , wherein said substrate comprises a flexible substrate.
9. The device of claim 1 , wherein said at least two or more wires of the plurality of nanowires have a sufficient density on the substrate to provide an operational current level of at least about 2 nanoamps.
10. The device of claim 1 , wherein said at least two or more nanowires of the plurality of nanowires have a sufficient density on the substrate to provide an operational current level of at least about 10 nanoamps.
11. The device of claim 1 , wherein each of said plurality of nanowires comprises one or more shell layers.
12. The device of claim 11 , wherein said one or more shell layers comprises an oxidized shell layer to thereby form a gate dielectric about said nanowires.
13. The device of claim 1 , wherein the at least two or more nanowires of the plurality of nanowires provides an electron mobility of greater than about 10 cm 2 /Vs between said first source and drain contacts.
14. The device of claim 1 , wherein said first gate contact is formed on said at least two or more nanowires.
15. The device of claim 1 , wherein the plurality of nanowires comprises a thin film of magnetic nanowires, a thin film of ferroelectric nanowires, a thin film of thermoelectric nanowires, a thin film of piezoelectric nanowires, a thin film of metallic nanowires, a thin film of transition metal oxide nanowires, or any combination thereof.
16. The device of claim 1 , wherein the plurality of nanowires are aligned on said substrate by a process selected from the group comprising spin-casting, Langmuir-Blodgett alignment, mechanical alignment, and flow-alignment.
17. The device of claim 1 , further comprising one or more gate dielectric layers deposited on said substrate between said first gate contact and said at least two or more nanowires.
18. An active matrix liquid crystal display comprising one or more devices of claim 1 .
19. A flat-panel display comprising one or more devices of claim 1 .
20. A memory device comprising one or more devices of claim 1 .
21. The device of claim 1 , wherein all of said plurality of nanowires in said thin film are semiconducting.