MOSFET having increased snap-back conduction uniformity
View Patent ↗According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.
1. A semiconductor structure comprising:
an NFET situated over a substrate;
a P+ substrate tie ring surrounding said NFET;
an N well ring situated between said NFET and said P+ substrate tie ring, such that said N well ring is situated adjacent to said NFET;
an N+ active ring situated over said N well ring, said N+ active ring is in direct contact with said P+ substrate tie ring and connects said P+ substrate tie ring to said N well ring;
wherein said N+ active ring connects said P+ substrate tie ring to said N well ring, and wherein said N well ring causes an increase in substrate resistance between said P+ substrate tie ring and at least one channel region of said NFET so as to increase snap-back conduction uniformity in said NFET.
2. The semiconductor structure of claim 1 wherein said N+ active ring comprises a salicide layer situated on an N+ diffusion region.
3. The semiconductor structure of claim 1 wherein said P+ substrate tie ring comprises a salicide layer situated on a P+ diffusion region.
4. The semiconductor structure of claim 2 wherein said salicide layer of said N+ active ring connects said N well ring to said P+ substrate tie ring.
5. A semiconductor structure comprising:
a first NFET situated over a substrate;
an N well ring surrounding said first NFET;
a P+ substrate tie ring situated between said N well ring and said first NFET, said P+ substrate ring surrounding said first NFET, said P+ substrate tie ring being in contact with said N well ring;
an N+ active ring situated over said N well ring, wherein said N+ active ring is in direct contact with said P+ substrate tie ring and connects said P+ substrate tie ring to said N well ring;
wherein said N well ring increases snap-back conduction uniformity in said first NFET, and wherein said P+ substrate tie ring is switchably coupled to a ground in a normal operating mode and switchably uncoupled from said ground during an occurrence of an ESD transient.
6. The semiconductor structure of claim 5 wherein said N+ active ring comprises salicide layer situated on an N+ diffusion region.
7. The semiconductor structure of claim 5 wherein said P+ substrate tie ring comprises a salicide layer situated on a P+ diffusion region.
8. The semiconductor structure of claim 5 further comprising a second NFET having a drain terminal, a source terminal, and a gate terminal, wherein said drain terminal is coupled to said P+ substrate tie ring, said source terminal is coupled to said ground, and said gate terminal is coupled to Vdd.
9. The semiconductor structure of claim 8 wherein said second NFET is configured to disconnect said P+ substrate tie ring from said ground during said occurrence of said ESD transient.
10. The semiconductor structure of claim 8 wherein said gate terminal is coupled to said Vdd by a resistor, wherein a time constant determined by said resistor and a gate capacitance of said second NFET is substantially greater than a rise time of said ESD transient.
11. A semiconductor structure comprising:
a first NFET situated over a substrate, said first NFET being a snap-back NFET;
an N well ring surrounding said first NFET;
a P+ substrate tie ring situated between said N well ring and said first NFET, said P+ substrate tie ring surrounding said first NFET, said P+ substrate tie ring being in contact with said N well ring;
an N+ active ring situated over said N well ring, wherein said N+ active ring is in direct contact with said P+ substrate tie ring and connects said N well ring to said P+ substrate tie ring;
a second NFET configured to couple said P+ substrate tie ring to a ground in a normal operating mode and to disconnect said P+ substrate tie ring from said ground during an occurrence of an ESD transient.
12. The semiconductor structure of claim 11 wherein said second NFET has a drain terminal, a source terminal, and a gate terminal, wherein said drain terminal is coupled to said P+ substrate tie ring, said source terminal is coupled to said ground, and said gate terminal is coupled to Vdd.
13. The semiconductor structure of claim 12 wherein said gate terminal is coupled to said Vdd by a resistor, wherein a time constant determined by said resistor and a gate capacitance of said second NFET is substantially greater than a rise time of said ESD transient.