Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor

1. A heterojunction bipolar transistor, comprising:

a collector region;

a base region made of a III-V semiconductor, above the collector region;

a first emitter region above the first base region;

a second emitter region above the first emitter region; and

an extrinsic region outside the second emitter region and above the first emitter region, the extrinsic region comprising: an etch stop region; an extrinsic base region; and an extrinsic cap region.

2. The transistor of claim 1 , wherein the first base region has a first thickness, and the extrinsic base region and extrinsic cap region combined have a second thickness, the first thickness being less than the second thickness.

3. The transistor of claim 1 , further comprising a dielectric region separating the second emitter region from the extrinsic region.

4. The transistor of claim 3 , wherein the dielectric region covers the extrinsic region in order to isolate the second emitter region from the extrinsic region.

5. The transistor of claim 1 , further comprising a contact region above the second emitter region.

6. The transistor of claim 1 , further comprising:

a substrate region;

a buffer region above the substrate region; and

a contact region above the buffer region,

the substrate region, buffer region and contact region being below the collector region.

7. The transistor of claim 1 , wherein, in use, the built-in potential of a junction between the first emitter region and the base region is less than 0.5 V.

8. A heterojunction bipolar transistor, comprising:

a collector region;

a first base region made of a III-V semiconductor, above the collector region;

a second base region made of a III-V semiconductor, above the first base region;

an emitter region directly overlying the second base region; and

an extrinsic region outside the emitter region and above the first base region, the extrinsic region comprising: an etch stop region; an extrinsic base region; and an extrinsic cap region.

9. The transistor of claim 8 , wherein the first base region and the second base region combined have a first thickness, and the first base region, the extrinsic base region and the extrinsic cap region combined have a second thickness, the first thickness being less than the second thickness.

10. The transistor of claim 8 , further comprising a dielectric region separating the emitter region from the extrinsic region.

11. The transistor of claim 8 , further comprising a contact region above the emitter region.

12. The transistor of claim 8 , further comprising:

a substrate region;

a buffer region above the substrate region; and

a contact region above the buffer region,

the substrate region, buffer region and contact region being below the collector region.

13. The transistor of claim 8 , wherein, in use, the built-in potential of a junction between the first emitter region and the base region is less than 0.5 V.

14. A method for fabricating a heterojunction bipolar transistor, comprising:

i) epitaxially growing a first layer sequence, the first layer sequence comprising:

a collector layer;

a base layer made of a III-V semiconductor, above the collector layer;

a first emitter layer above the base layer;

an etch stop layer above the first emitter layer;

an extrinsic base layer above the etch stop layer; and

an extrinsic cap layer above the extrinsic base layer,

ii) etching away a portion of the first layer sequence thereby forming an etched away portion and a non-etched away portion of the first layer sequence, the etched away portion comprising:

a portion of the etch stop layer;

a portion of the extrinsic base layer; and

a portion of the extrinsic cap layer,

iii) epitaxially growing a second layer sequence, the second layer sequence comprising:

a second emitter layer above the first emitter layer; and

a contact layer above the second emitter layer.

15. The method of claim 14 , further comprising: isolating the second layer sequence from the non-etched away portion of the first layer sequence.

16. The method of claim 14 , wherein the first layer sequence further comprises:

a substrate region;

a buffer region above the substrate region; and

a contact region above the buffer region,

the substrate region, buffer region and contact region being below the collector region.

17. A method for fabricating a heterojunction bipolar transistor, comprising:

i) epitaxially growing a first layer sequence, the first layer sequence comprising:

a collector layer;

a first base layer made of a III-V semiconductor compound, above the collector layer;

an etch stop layer above the first base layer;

an extrinsic base layer made of a III-V semiconductor compound, above the etch stop layer; and

an extrinsic cap layer above the extrinsic base layer,

ii) etching away a portion of the first layer sequence thereby forming an etched away portion and a non-etched away portion of the first layer sequence, the etched away portion comprising:

a portion of the etch stop layer;

a portion of the extrinsic base layer; and

a portion of the extrinsic cap layer,

iii) epitaxially growing a second layer sequence, the second layer sequence comprising:

a second base layer above the first base layer;

an emitter layer above the second base layer; and

an emitter contact layer above the emitter layer.

18. The method of claim 17 , further comprising: isolating the second layer sequence from the non-etched away portion of the first layer sequence.

19. The method of claim 17 , wherein the first layer sequence further comprises:

a substrate region;

a buffer region above the substrate region; and

a contact region above the buffer region,

the substrate region, buffer region and contact region being below the collector region.