Light emitting panel and light emitting display

1. A display device including a plurality of scan lines provided in a first direction for transmitting select signals, a plurality of data lines provided in a second direction for transmitting data signals, and a plurality of pixel circuits respectively coupled to the scan lines and the data lines, wherein at least one of the pixel circuits comprises:

a first capacitor for charging a voltage corresponding to one of the data signals;

a first transistor for outputting a current corresponding to the voltage charged in the first capacitor;

a first emit element and a second emit element for outputting light corresponding to the current output by the first transistor;

a first emit control transistor coupled between the first transistor and the first emit element;

a second emit control transistor coupled between the first transistor and the second emit element;

a first emit control line coupled to a control electrode of the first emit control transistor; and

a second emit control line coupled to a control electrode of the second emit control transistor,

wherein a first semiconductor layer for forming the first emit control transistor and a second semiconductor layer for forming the second emit control transistor are branched from a third semiconductor layer for forming the first transistor and are formed as a single body with the third semiconductor layer.

2. The display device of claim 1 , wherein the first and second emit control lines are formed to be substantially adjacent and parallel with each other.

3. The display device of claim 2 , wherein at least parts of the first and second semiconductor layers are formed to be substantially parallel with each other.

4. The display device of claim 1 , wherein the at least one of the pixel circuits further comprises:

a second transistor for diode-connecting the first transistor;

a third transistor having a first transistor electrode coupled to a first electrode of the first capacitor, and a second transistor electrode coupled to a second electrode of the first capacitor; and

a second capacitor having a first capacitor electrode coupled to the second transistor electrode of the third transistor, and a second capacitor electrode coupled to a control electrode of the first transistor.

5. A display device including a plurality of scan lines provided in a first direction for transmitting select signals, a plurality of data lines provided in a second direction for transmitting data signals, and a plurality of pixel circuits respectively coupled to the scan lines and the data lines, wherein at least one of the pixel circuits comprises:

a first capacitor for charging a voltage corresponding to one of the data signals;

a first transistor having a control electrode coupled to a first capacitor electrode of the first capacitor, and a first electrode coupled to a second capacitor electrode of the first capacitor, the first transistor outputting a current corresponding to the voltage charged in the first capacitor;

a first emit element, a second emit element, and a third emit element for outputting light corresponding to the current output by the first transistor;

a first emit control transistor coupled between the first transistor and the first emit element;

a second emit control transistor coupled between the first transistor and the second emit element;

a third emit control transistor coupled between the first transistor and the third emit element;

a first emit control line coupled to a control electrode of the first emit control transistor;

a second emit control line coupled to a control electrode of the second emit control transistor; and

a third emit control line coupled to a control electrode of the third emit control transistor,

wherein a first semiconductor layer for forming the first emit control transistor, a second semiconductor layer for forming the second emit control transistor, and a third semiconductor layer for forming the third emit control transistor are branched from a fourth semiconductor layer for forming the first transistor and are formed as a single body with the fourth semiconductor layer.

6. The display device of claim 5 , wherein at least parts of the first, second, and third semiconductor layers are formed to be substantially parallel with each other so that the first, second, and third semiconductor layers in a plane has a substantial m shape.

7. The display device of claim 5 , wherein the first transistor comprises a p-channel transistor, and the emit control transistors comprise p-channel transistors.

8. The display device of claim 5 , wherein the first transistor comprises a p-channel transistor, and the emit control transistors comprise n-channel transistors.

9. The display device of claim 8 , wherein the display device further comprises a junction electrode and a contract hole and wherein the junction electrode is formed at an edge region of the fourth semiconductor layer and the first, second, and third semiconductor layers through the contact hole, and a current output by the first transistor is transmitted to the emit control transistors through the junction electrode.

10. A display panel including, in an array format, a plurality of scan lines provided in a first direction for transmitting select signals, a plurality of data lines provided in a second direction for transmitting data signals, and a plurality of pixel circuits respectively coupled to the scan lines and the data lines, wherein at least one of the pixel circuits comprises:

a capacitor for charging a voltage corresponding to one of the data signals;

a first transistor having a control electrode coupled to a first capacitor electrode of the capacitor, and a first electrode coupled to a second capacitor electrode of the capacitor, the first transistor outputting a current corresponding to the voltage charged in the capacitor;

a first emit element and a second emit element for outputting light corresponding to the current output by the first transistor;

a first emit control transistor coupled between the first transistor and the first emit element;

a second emit control transistor coupled between the first transistor and the second emit element;

a first emit control line coupled to a control electrode of the first emit control transistor and arranged to be substantially parallel with at least one of the scan lines; and

a second emit control line coupled to a control electrode of the second emit control transistor and arranged to be substantially parallel with the at least one of the scan lines;

wherein a pixel area in which the at least one of the pixel circuits is arranged comprises:

a semiconductor layer including a first semiconductor layer region for forming the first transistor, a second semiconductor layer region for forming the first emit control transistor, and a third semiconductor layer region for forming the second emit control transistor, the second and third semiconductor layer regions being branched from the first semiconductor layer region and formed as a single body with the first semiconductor layer region;

a first insulation layer formed on the semiconductor layer;

a metallic layer formed on a portion of the first insulation layer on the second and third semiconductor layer regions, and including a first metallic layer region for forming the first emit control line and a second metallic layer region for forming the second emit control line; and

a second insulation layer formed on the first insulation layer and the metallic layer.

11. The display panel of claim 10 , wherein the first and second emit control lines are arranged to be substantially adjacent and parallel with each other, and at least parts of the second and third semiconductor layer regions are arranged to be substantially parallel with at least one of the data lines.

12. The display panel of claim 10 , wherein regions other than a channel region of the second and third semiconductor layer regions are doped with p+ impurities.

13. The display panel of claim 10 , wherein regions other than a channel region of the second and third semiconductor layer regions are doped with n+ impurities.

14. The display panel of claim 13 , wherein the pixel area in which the at least one of the pixel circuits is arranged further comprises a contact hole for penetrating the first and second insulation layers and a junction electrode and wherein the contact hole is formed at an edge of the second and third semiconductor layer regions and the first semiconductor layer region, and the junction electrode is formed within the contact hole.

15. A display panel including, in an array format, a plurality of scan lines provided in a first direction for transmitting select signals, a plurality of data lines provided in a second direction for transmitting data signals, and a plurality of pixel circuits respectively coupled to the scan lines and the data lines, wherein at least one of the pixel circuit comprises:

a capacitor for charging a voltage corresponding to one of the data signals;

a first transistor for outputting a current corresponding to the voltage charged in the capacitor;

a first emit element, a second emit element, and a third emit element for outputting light of different colors based on the current output by the first transistor;

a first emit control transistor coupled between the first transistor and the first emit element;

a second emit control transistor coupled between the first transistor and the second emit element;

a third emit control transistor coupled between the first transistor and the third emit element;

a first emit control line coupled to a control electrode of the first emit control transistor;

a second emit control line coupled to a control electrode of the second emit control transistor; and

a third emit control line coupled to a control electrode of the third emit control transistor,

wherein a pixel area in which the at least one of the pixel circuits is arranged comprises:

a semiconductor layer including a first semiconductor layer region for forming the first transistor, a second semiconductor layer region for forming the first emit control transistor, a third semiconductor layer region for forming the second emit control transistor, and a fourth semiconductor layer region for forming the third emit control transistor, the second, third, and fourth semiconductor layer regions being branched from the first semiconductor layer region and formed as a single body with the first semiconductor layer region;

a first insulation layer formed on the semiconductor layer;

a metallic layer formed on a portion of the first insulation layer on the second, third, and fourth semiconductor layer regions, and including a first metallic layer region for forming the first emit control line, a second metallic layer region for forming the second emit control line, and a third metallic layer region for forming the third emit control line; and

a second insulation layer formed on the first insulation layer and the metallic layer.

16. The display panel of claim 15 , wherein at least parts of the second, third, and fourth semiconductor layer regions are arranged to be substantially parallel with at least one of the data lines.