Method and system for selective equalization enablement based on modulation type

1. A method for processing a radio frequency (RF) signal, the method comprising:

performing by one or more processors or circuits, functions comprising:

receiving signals via an RF channel;

detecting a modulation type for at least a portion of said received signals;

determining whether to enable or disable an equalization circuit for processing said at least a portion of said received signals based on said detected modulation type;

selecting one of a plurality of inputs to a selector based on said detected modulation type, wherein said plurality of inputs comprise said at least a portion of said received signals and an output signal generated by said equalization circuit;

generating a phase signal based on said selected one of said plurality of inputs; and

generating binary bits based on said generated phase signal.

2. The method according to claim 1 , comprising determining a data rate of said at least a portion of said received signals based on said detected modulation type.

3. The method according to claim 2 , comprising enabling said equalization circuit for processing said at least a portion of received signals based on said determined data rate.

4. The method according to claim 2 , comprising selecting said at least a portion of said received signals based on said determined data rate.

5. The method according to claim 2 , comprising enabling said equalization circuit for said processing of said at least a portion of said received signals when said determined data rate is at least 1 megabit per second.

6. The method according to claim 2 , comprising disabling said equalization circuit for said processing of said at least a portion of said received signals when said determined data rate is less than 1 megabit per second.

7. The method according to claim 1 , comprising selectively configuring said equalization circuit in a power ON state when said equalization circuit is enabled.

8. The method according to claim 1 , comprising selectively configuring said equalization circuit in a power OFF state when said equalization circuit is disabled.

9. The method according to claim 1 , comprising selecting said generated output signal when said equalization circuit is enabled.

10. The method according to claim 1 , comprising selecting said at least a portion of said received signals when said equalization circuit is disabled.

11. A system for processing a radio frequency (RF) signal, the system comprising:

one or more circuits that are operable to receive signals via an RF channel;

said one or more circuits are operable to detect a modulation type for at least a portion of said received signals;

said one or more circuits are operable to determine whether to enable or disable an equalization circuit for processing said at least a portion of said received signals based on said detected modulation type;

said one or more circuits are operable to select one of a plurality of inputs to a selector based on said detected modulation type, wherein said plurality of inputs comprise said at least a portion of said received signals and an output signal generated by said equalization circuit;

said one or more circuits are operable to generate a phase signal based on said selected one of said plurality of inputs; and

said one or more circuits are operable to generate binary bits based on said generated phase signal.

12. The system according to claim 11 , wherein said one or more circuits are operable to determine a data rate of said at least a portion of said received signals based on said detected modulation type.

13. The system according to claim 12 , wherein said one or more circuits are operable to enable said equalization circuit for processing said at least a portion of said received signals based on said determined data rate.

14. The system according to claim 12 , wherein said one or more circuits are operable to select said at least a portion of said received signals based on said determined data rate.

15. The system according to claim 12 , wherein said one or more circuits are operable to enable said equalization circuit for said processing of said at least a portion of said received signals when said determined data rate is at least 1 megabit per second.

16. The system according to claim 12 , wherein said one or more circuits is operable to disable said equalization circuit for said processing of said at least a portion of said received signals when said determined data rate is less than 1 megabit per second.

17. The system according to claim 11 , wherein said one or more circuits are operable to selectively configure said equalization circuit in a power ON state when said equalization circuit is enabled.

18. The system according to claim 11 , wherein said one or more circuits are operable to configure said equalization circuit in a power OFF state when said equalization circuit is disabled.

19. The system according to claim 11 , wherein said one or more circuits are operable to select said generated output signal when said equalization circuit is enabled.

20. The system according to claim 11 , wherein said one or more circuits are operable to select said at least a portion of said received signals when said equalization circuit is disabled.

21. The system according to claim 11 , wherein said one or more circuits comprise a processor.