Program stack handling
View Patent ↗Systems, methods, and device are provided for program stack handling. One method embodiment includes recognizing that a fault has occurred because a particular address range in a memory stack has been accessed. The method includes evaluating a current utilized size of regions in the memory stack. A particular address range between the current utilized size of regions in the memory stack is then relocated.
1. A method for handling a memory stack, comprising:
providing a first address range in a memory stack for a first program stack;
providing a second address range in the memory stack for a second program stack;
providing a particular address range between the first address range and the second address range as a guard page for both the first program stack and the second program stack;
recognizing that a fault has occurred because the particular address range in the memory stack has been accessed by either the first program stack or the second program stack;
evaluating a currently utilized size of the first and the second program stacks; and
relocating the particular address range to a new location between the first and the second program stacks;
wherein the providing the particular address range includes providing a first empty region between the first address range and the particular address range, and a second empty region between the second address range and the particular address range.
2. The method of claim 1 , wherein the first address range includes a heap region.
3. The method of claim 1 , wherein relocating the particular address range includes relocating the particular address range between the first and the second program stacks with a third empty region between the first program stack and the particular address range, and a fourth empty region between the second program stack and the particular address range.
4. A computing device, comprising:
a processor;
a memory coupled to the processor; and
program instructions provided to the memory and executable by the processor to:
provide a first address range in a memory stack for a first program stack;
provide a second address range in the memory stack for a second program stack;
provide a particular address range between the first address range and the second address range with a first empty region between the first address range and the particular address range, and a second empty region between the second address range and the particular address range;
generate a fault when the particular address range is accessed by either the first program stack or the second program stack;
responsive to the fault, evaluate a current utilized size of each of the first and the second program stacks; and
relocate the particular address range to a new location between the first and the second program stacks.
5. The computing device of claim 4 , wherein the particular address range is a guard page.
6. The computing device of claim 4 , wherein the second address range includes a heap region.
7. The computing device of claim 4 , wherein the new location is closer to the first program stack, as compared to a corresponding location before the relocating, if the the particular address range is accessed by the second program stack.
8. The computing device of claim 4 , wherein the new location is closer to the second program stack if particular address range is accessed by the first program stack.
9. A computing device, comprising:
a processor;
a memory coupled to the processor;
means for:
providing a first address range in a memory stack for a first program stack;
providing a second address range in the memory stack for a second program stack;
providing a particular address range between the first address range and the second address range as a guard page for both the first program stack and the second program stack;
recognizing that a fault has occurred because the particular address range has been accessed by either the first program stack or the second program stack;
evaluating a currently utilized size of the first and the second program stacks; and
relocating the particular address range to a new location between the first and the second program stacks;
and means for providing a first empty region between the first address range and the particular address range, and a second empty region between the second address range and the particular address range when the particular address range is provided between the first address range and the second address range.
10. The computing device of claim 9 , wherein the means for recognizing that the fault has occurred includes program instructions in a kernel's fault handling code that execute to recognize that the fault has occurred because a guard page in the particular address range has been accessed by at least one of the first and second program stacks.
11. The computing device of claim 10 , wherein the means includes program instructions located in an application space to:
receive a fault signal from the kernel's fault handling code;
evaluate whether the guard page should be adjusted; and
signal the kernel's fault handling code to relocate the guard page based on the evaluation.
12. The computing device of claim 9 , including means for providing a third empty region between the first program stack and the relocated particular address range, and a fourth empty region between the second program stack and the relocated particular address range.