One-time programmable circuit exploiting BJT h
View Patent ↗A one-time programmable circuit uses forced BJT h FE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.
1. A method of providing an output signal comprising:
providing a first bipolar transistor having a nominal h FE ;
providing a second bipolar transistor having a nominal h FE ;
providing a first current mirror having a input coupled to a base of the first bipolar transistor and an outputed coupled to a base of the second bipolar transistor;
providing a second current mirror having an input coupled to a collector of the first bipolar transistor and an output coupled to a collector of the second bipolar transistor;
providing an output signal at the output of the second current mirror; and
optionally degrading the h FE of the second bipolar transistor to change the output signal from a first state to a second state.
2. The method of claim 1 wherein the second state of the output signal is permanent.
3. The method of claim 1 wherein the first and second states of the output signal comprise digital logic states.
4. The method of claim 1 wherein providing a first bipolar transistor and providing a second bipolar transistor comprises providing an NPN bipolar transistor.
5. The method of claim 1 wherein the h FE of the second bipolar transistor is degraded by generating a negative V BE for a predetermined length of time.
6. The method of claim 5 wherein the negative V BE is obtained by the application of a voltage to the emitter of the second bipolar transistor.
7. The method of claim 5 wherein the negative VBE is obtained by the application of a current to the emitter of the second bipolar transistor.
8. The method of claim 5 wherein the absolute value of the negative VBE is about two to five volts.
9. The method of claim 5 wherein the predetermined length of time is about 20 to 30 milliseconds.
10. The method of claim 5 wherein the h FE is degraded in excess of 80%.
11. A circuit for providing an output signal comprising:
a first bipolar transistor having a nominal h FE ;
a second bipolar transistor having a nominal h FE ;
a first current mirror having an input coupled to a base of the first bipolar transistor and an output coupled to a base of the second bipolar transistor;
a second current mirror having an input coupled to a collector of the first bipolar transistor and an output coupled to a collector of the second bipolar transistor;
an output signal at the output of the second current mirror; and
circuitry for optionally degrading the h FE of the second bipolar transistor to change the output signal from a first state to a second state.
12. The circuit of claim 11 wherein the second state of the output signal is permanent.
13. The circuit of claim 11 wherein the first and second states of the output signal comprise digital logic states.
14. The circuit of claim 11 wherein the first bipolar transistor and the second bipolar transistor each comprise an NPN bipolar transistor.
15. The circuit of claim 11 wherein the h FE of the second bipolar transistor is degraded by generating a negative V BE for a predetermined length of time.
16. The circuit of claim 15 wherein the negative V BE is obtained by the application of a voltage to the emitter of the second bipolar transistor.
17. The circuit of claim 15 wherein the negative VBE is obtained by the application of a current to the emitter of the second bipolar transistor.
18. The circuit of claim 15 wherein the absolute value of the negative VBE is about two to five volts.
19. The circuit of claim 15 wherein the predetermined length of time is about 20 to 30 milliseconds.
20. The circuit of claim 15 wherein the h FE is degraded in excess of 80%.
21. A one time programmable circuit for providing a plurality of digital output signals comprising:
a plurality of bipolar transistors each having a nominal h FE including a first bipolar transistor and a plurality of bipolar transistors;
a first current mirror having an inputs coupled to a base of each of the first bipolar transistor and a plurality of outputs coupled to a base of the remaining bipolar transistors;
a second current mirror having an input coupled to a collector of the first bipolar transistors and a plurality of outputs coupled to a collector of each of the remaining bipolar transistors;
a plurality of output signals at the outputs of the second current mirror; and
circuitry for selectively degrading the h FE of the remaining bipolar transistors to change the corresponding output signals from a permanent first logic state to a permanent second logic state.