Self-biased darlington amplifier
View Patent ↗An apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.
1. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
a bias circuit coupled between a base of an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (i) a bias transistor, (ii) a bypass capacitor, and (iii) a blocking resistor; and
a parallel feedback resistor coupled between said output node and said input node, wherein said parallel feedback resistor is coupled in parallel with said bias circuit.
2. The apparatus according to claim 1 , wherein said blocking resistor is connected between a base of said bias transistor and a base of said output transistor.
3. The apparatus according to claim 1 , wherein said bias circuit further comprises:
an emitter bias resistor configured to set a class A, AB, B or other quiescent bias state.
4. The apparatus according to claim 2 , further comprising:
a low noise filter implementation (i) comprising at least one additional bypass capacitor and (ii) coupled between said bias transistor and said input node.
5. The apparatus according to claim 1 , further comprising:
an isolation resistor coupled between said input node and a collector of said bias transistor.
6. The apparatus according to claim 1 , wherein said Darlington transistor pair and said bias transistor are implemented using high electron mobility transistor (HEMT) technology.
7. The apparatus according to claim 1 , wherein said Darlington transistor pair comprises an input transistor coupled between said input node and said output transistor.
8. The apparatus according to claim 7 , further comprises:
a first bias resistor coupled to said input transistor.
9. The apparatus according to claim 1 , further comprises:
a second bias resistor coupled to said output transistor.
10. The apparatus according to claim 1 , wherein said apparatus comprises a self bias Darlington amplifier.
11. The apparatus according to claim 1 , wherein said bias transistor comprises a collector coupled to said input node.
12. The apparatus according to claim 1 , wherein said Darlington transistor pair comprises a distributed Darlington amplifier.
13. An apparatus comprising:
a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
means for coupling between a base of an output transistor of said Darlington transistor pair and said input node comprising (i) a bias transistor, (ii) a bypass capacitor, and (iii) a blocking resistor; and
a parallel feedback resistor coupled between said input node and said output node in parallel with said coupling means.
14. A method for self-biasing a Darlington amplifier comprising the steps of:
(A) implementing a Darlington transistor pair configured to generate an output signal at an output node in response to an input signal received through an input node;
(B) coupling a bias circuit between a base of an output transistor of said Darlington transistor pair and said input node, said bias circuit comprising (a) a bias transistor, (b) a bypass capacitor, (c) a blocking resistor; and
(C) coupling a resistor between said input node and a said output node in parallel with said bias circuit.
15. The method according to claim 14 , wherein said blocking resistor is connected between a base of said bias transistor and a base of said output transistor.
16. The method according to claim 14 , wherein said bias circuit further comprises:
an emitter bias resistor configured to set a class A, AB, B or other quiescent bias state.
17. The method according to claim 14 , further comprising:
implementing a low noise filter (i) comprising at least one bypass capacitor and (ii) coupled between said bias transistor and said input node.
18. The method according to claim 14 , further comprising:
implementing a bias feedback resistor coupled between a collector of said bias transistor and said output node.
19. The method according to claim 18 , further comprising:
generating a reference current with said bias circuit and said bias feedback resistor to establish a mirrored relationship between said reference current and a current output of said output transistor.
20. The method according to claim 19 , further comprising:
scaling the size an emitter bias resistor by a predetermined value to the size of a series feedback resistor to establish said mirrored relationship.