Audio digital to analog converter with harmonic suppression
View Patent ↗A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.
1. A digital to analog converter (DAC) comprising:
a first circuit configured to remove even harmonic errors from an output signal, the first circuit a first threshold value and a second threshold value, where the two threshold inputs define a threshold range that varies, and a switching circuit configured to reverse the threshold values between the first and second threshold inputs;
a second circuit configured to remove odd harmonics from an output signal, the second circuit configured to receive a third threshold value and a fourth threshold value, wherein the third and fourth values vary, and a switching circuit configured to reverse the threshold values between the third and fourth threshold inputs; and
an amplifier configured to receive an output from the first circuit and an inverted output from the second circuit, and configured to transmit an output signal.
2. A digital to analog converter comprising:
a first circuit configured to remove even harmonic errors;
a second circuit configured to eliminate odd harmonic errors; and
a differential amplifier configured to receive an output from the first circuit and an inverted output of the second circuit and to generate an output signal.
3. A DAC according to claim 2 , wherein the first circuit has a first DAC module configured with a first threshold input for receiving a first threshold value and a second threshold input for receiving a second threshold value.
4. A DAC according to claim 2 , wherein the first circuit has a first DAC module configured with a first threshold input for receiving a first threshold value and a second threshold input for receiving a second threshold value, where the two threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold.
5. A DAC according to claim 2 , wherein the first circuit has a switching circuit configured to reverse the threshold values between the first and second threshold inputs.
6. A DAC according to claim 2 , the second circuit having a second DAC module configured with a third threshold input for receiving a third threshold value and a fourth threshold input for receiving a fourth threshold value, where the third and fourth threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold, and a switching circuit configured to reverse the threshold values between the first and second threshold inputs.
7. A DAC according to claim 2 , the second circuit having a second DAC module configured with a third threshold input for receiving a third threshold value and a fourth threshold input for receiving a fourth threshold value.
8. A DAC according to claim 7 , wherein the third and fourth threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold.
9. According to claim 7 , wherein the second circuit has a switching circuit configured to reverse the threshold values between the first and second threshold inputs.
10. A method for making a digital to analog conversion, comprising:
removing even harmonic errors with a first circuit;
removing odd harmonic errors with a second circuit; and
receiving an output from the first circuit and an inverted output of the second circuit and generating an output signal.
11. A method according to claim 10 , further comprising receiving a first threshold value a second threshold value.
12. A method according to claim 10 , further comprising receiving a first threshold value a second threshold value, where the two threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold.
13. A method according to claim 10 , further comprising reversing the threshold values between the first and second threshold inputs.
14. A method according to claim 10 , further comprising reversing the threshold values between the first and second threshold inputs with a switching circuit.
15. A method according to claim 10 , wherein the output signal is generated by a differential amplifier.
16. A method according to claim 11 , further comprising receiving a third threshold value with third threshold input and a fourth threshold input with a fourth threshold input, where the third and fourth threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold.
17. A method according to claim 12 wherein the third and fourth threshold value is received by a second DAC configured with a third and fourth threshold input.
18. A method according to claim 17 , wherein the third and fourth thresholds are received by a second DAC module, and wherein the method further comprises reversing the threshold values between the first and second threshold inputs.
19. A method according to claim 10 , further comprising receiving a third threshold value and a fourth threshold input for receiving a fourth threshold value with the second circuit.
20. A method according to claim 10 , where the third and fourth threshold inputs define a threshold range that varies between a low voltage threshold and a high voltage threshold.
21. A method according to claim 10 , further comprising reversing the threshold values between the first and second threshold inputs with switching circuit in the second circuit.