Chip scale surface mounted device and process of manufacture
View Patent ↗A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
1. A process for fabricating a semiconductor device package, comprising:
covering a side of a MOSgated device wafer with a passivation layer, said passivation layer being capable of serving as a solder mask;
forming openings in said passivation layer to produce a plurality of spaced exposed surface areas of underlying source and a similar opening to expose underlying gate electrode of each die, wherein said openings in said passivation layer reach an underlying solderable top metal;
singulating said wafer into individual die; and
electrically attaching an individual die at a drain side thereof to a drain clip.
2. A process according to claim 1 , wherein said solderable top metal is comprised of titanium/tungsten/nickel/silver metal.
3. A process according to claim 1 , wherein said drain clip is U-shaped.
4. A process according to claim 1 , wherein said drain clip is cup shaped.
5. A process according to claim 1 , wherein said drain clip is plated.
6. A process according to claim 1 , wherein said die is electrically attached to said drain clip by a conductive epoxy or solder.
7. A process according to claim 1 , wherein said drain clip includes at least one leg and a bottom portion of said leg being coplanar with a source-side of said die.
8. A process according to claim 1 , further comprising overmolding at least part of said assembly of said die and said drain clip.
9. A process according to claim 1 , wherein said passivation layer is comprised of an epoxy.
10. A process according to claim 9 , wherein said wafer is covered by spinning.
11. A process according to claim 9 , wherein said wafer is covered by screening.
12. A process according to claim 9 , wherein said wafer is covered by depositing a liquid epoxy.
13. A process according to claim 1 , wherein said passivation is comprised of a photosensitive epoxy.
14. A process according to claim 1 , wherein said passivation is comprised of silicon nitride.
15. A process for fabricating a semiconductor device package, comprising:
covering a side of a MOSgated device wafer with a passivation layer, said passivation layer being capable of serving as a solder mask and a plating resist;
forming openings in said passivation layer to produce a plurality of spaced exposed surface areas of underlying source and a similar opening to expose underlying gate electrode of each die;
plating said underlying source and gate electrodes using said passivation layer as a plating resist, thereby forming a solderable contact on said source electrode and a solderable contact on said gate electrode;
singulating said wafer into individual die; and
electrically attaching an individual die at drain side thereof to a drain clip.
16. A process according to claim 15 , wherein said source and said gate electrodes are plated with nickel and followed by either gold flash, or copper, or tin, and then with a solderable metal.
17. A process according to claim 15 , wherein said solderable metal is silver.
18. A process according to claim 15 , wherein said drain clip is U-shaped.
19. A process according to claim 15 , wherein said drain clip is cup shaped.
20. A process according to claim 15 , wherein said drain clip is plated.
21. A process according to claim 15 , wherein said die is electrically attached to said drain clip by a conductive epoxy or solder.
22. A process according to claim 15 , wherein said drain clip includes at least one and leg a bottom portion of said leg being coplanar with a source-side of said die.
23. A process according to claim 15 , further comprising overmolding at least part of said assembly of said die and said drain clip.
24. A process according to claim 15 , wherein said passivation layer is comprised of an epoxy.
25. A process according to claim 24 , wherein said wafer is covered by spinning.
26. A process according to claim 24 , wherein said wafer is covered by screening.
27. A process according to claim 24 , wherein said wafer is covered by depositing a liquid epoxy.
28. A process according to claim 15 , wherein said passivation is comprised of a photosensitive epoxy.
29. A process according to claim 15 , wherein said passivation is comprised of silicon nitride.