Transceiver module and integrated circuit with clock and data recovery clock diplexing
View Patent ↗An integrated circuit. The integrated circuit is usable in a transceiver module. The integrated circuit includes an input port that is configured to receive a data stream. A clock port on the integrated circuit is configured to receive a reference clock diplexed with another signal or voltage used by the integrated circuit. An eye opening circuit is connected to the input port and clock. The eye opening circuit is configured to retime the data stream received at the input port. An output port is connected to the eye opening circuits The output port is configured to transmit a retimed signal from the eye opening circuit to a device external to the integrated circuit. A bypass circuit is connected to the input port and the output port. The bypass circuit may selectively bypass the eye opening circuit.
1. An integrated circuit usable in a transceiver module, the integrated circuit comprising:
an input port configured to receive a data stream;
a clock port configured to receive a reference clock signal diplexed with another signal or voltage used by the integrated circuit;
an eye opening circuit coupled to the input port and clock port, the eye opening circuit configured to retime the data stream received at the input port;
an output port coupled to the eye opening circuit, the output port configured to transmit a retimed signal from the eye opening circuit to a device external to the integrated circuit; and
a bypass circuit coupled to the input port and the output port, wherein the bypass circuit is configured to selectively bypass the eye opening circuit.
2. The integrated circuit of claim 1 , wherein the clock port comprises a Vcc port configured to receive a supply voltage for the integrated circuit.
3. The integrated circuit of claim 1 , wherein the clock port comprises at least one of a rate control pin, a transmit disable pin, a Loss of Signal pin, and a transmit fault pin.
4. The integrated circuit of claim 1 , wherein the bypass circuit is selected to bypass the eye opening circuit upon receipt of a loss of signal (LOS) signal.
5. The integrated circuit of claim 1 , wherein the bypass circuit is selected to bypass the eye opening circuit upon receipt of a loss of lock (LOL) signal.
6. The integrated circuit of claim 1 , wherein the bypass circuit is selected to bypass the eye opening circuit when a data rate of a data stream at the input port is below a predetermined threshold.
7. The integrated circuit of claim 1 , further comprising pin connections complying with the SFP Multi Source Agreement.
8. The integrated circuit of claim 1 , wherein the eye-opener circuit comprises an adaptive equalizer configured to remove channel effects.
9. An integrated circuit usable in a transceiver module, the integrated circuit comprising:
an input port configured to receive a data stream;
a clock port configured to receive a reference clock signal diplexed with another signal or voltage used by the integrated circuit, wherein the clock port comprises a Vcc port configured to receive a supply voltage for the integrated circuit;
an eye opening circuit coupled to the input port and clock port, the eye opening circuit configured to retime the data stream received at the input port;
an output port coupled to the eye opening circuit, the output port configured to transmit a retimed signal from the eye opening circuit to a device external to the integrated circuit, wherein the clock port is configured to receive a clock signal diplexed with Vcc when the clock signal is about 10% or less the magnitude of Vcc.
10. A method of handling data comprising:
receiving a data stream;
receiving a clock signal that has been diplexed with another signal or voltage;
selectively retiming the data stream using the clock signal or bypassing retiming the data stream;
transmitting the retimed or bypassed data stream; and
powering down a clock and data recovery circuit when the act of bypassing retiming the data stream is performed.
11. The method of claim 10 , further comprising receiving a loss of lock (LOL) signal to selectively bypass retiming the data stream.
12. The method of claim 10 , further comprising receiving a loss of signal (LOS) signal to selectively bypass retiming the data stream.
13. The method of claim 10 , wherein receiving a clock signal comprises receiving the clock signal diplexed with a Vcc voltage.
14. The method of claim 10 , wherein receiving a clock signal comprises receiving the clock signal diplexed with at least one of a rate control signal, a transmit disable signal, a Loss of Signal signal, and a transmit fault signal.
15. The method of claim 10 , further comprising equalizing the data stream to remove channel effects.