Semiconductor device
View Patent ↗The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
1. A semiconductor device comprising:
a first memory array including a first bit line, a first word line across the first bit line, and a plurality of first memory cells coupled to the first bit line;
a second memory array including a second bit line, a third bit line, a second word line across the second and third bit lines, a plurality of second memory cells coupled to the second bit line, and a plurality of third memory cells coupled to the second bit line;
a first pre-amplifier coupled to the first bit line;
a second pre-amplifier coupled to the second bit line; a third pre-amplifier coupled to the third bit line;
a first local bit line coupled between the first and second pre-amplifiers;
a second local bit line coupled to the third pre-amplifier;
a first sense amplifier coupled to the first local bit line and amplifying a signal, which is outputted from the first or second pre-amplifier, to a first potential or a second potential;
a second sense amplifier coupled to the second local bit line and amplifying a signal, which is outputted from the third pre-amplifier, to the first potential or the second potential;
a first precharge circuit coupled to the first bit line and supplying a first precharge potential between the first and second potential to the first bit line;
a second precharge circuit coupled to the second bit line and supplying the first precharge potential to the second bit line;
a third precharge circuit coupled to the third bit line and supplying the first precharge potential to the third bit line;
a fourth precharge circuit coupled to the first local bit line and supplying a second precharge potential higher than the first precharge potential to the first local bit line; and
a fifth precharge circuit coupled to the second local bit line and supplying the second precharge potential to the second local bit line,
wherein the first sense amplifier is arranged between the first memory array and the second memory array, and
wherein the second memory array is arranged between the first sense amplifier and the second sense amplifier.
2. A semiconductor device according to claim 1 ,
wherein the first precharge potential is a half potential of the first precharge potential, and
wherein the second precharge potential is the first potential.
3. A semiconductor device according to claim 1 , further comprising:
a first switch circuit coupled between the first bit line and the first local bit line;
a second switch circuit coupled between the second bit line and the first local bit line; and
a third switch circuit coupled between the third bit line and the second local bit line.
4. A semiconductor device according to claim 1 ,
wherein the first switch circuit becomes an OFF state to read out from one of the plurality of first memory cells, and becomes an ON state to write into one of the plurality of first memory cells,
wherein the second switch circuit becomes an OFF state to read out from one of the plurality of second memory cells, and becomes an ON state to write into one of the plurality of second memory cells, and
wherein the third switch circuit becomes an OFF state to read out from one of the plurality of third memory cells, and becomes an ON state to write into one of the plurality of third memory cells.
5. A semiconductor device according to claim 1 , further comprising:
a third local bit line coupled between the first pre-amplifier and the second pre-amplifier; and
a fourth local bit line coupled to the third pre-amplifier,
wherein the first pre-amplifier makes a difference between a potential of the first local bit line and a potential of the third local bit line by discharging the first and third local bit lines, which are precharged to the second precharge potential, according to the information held in selected one of the plurality of first memory cells,
wherein the second pre-amplifier makes a difference between the pot ential of the first local bit line and the potential of the third local bit line by discharging the first and third local bit lines, which are precharged to the second precharge potential, according to the information held in selected one of the plurality of second memory cells,
wherein the third pre-amplifier makes a difference between a potential of the second local bit line and a potential of the fourth local bit line by discharging the second and fourth local bit lines, which are prechareged to the second precharge potential, according to the information held in selected one of the plurality of third memory cells.
6. A semiconductor device according to claim 5 ,
wherein the first sense amplifier amplifies the difference between the potential of the first local bit line and the potential of the third local bit line, and
wherein the second sense amplifier amplifies the difference between the potential of the second local bit line and the potential of the fourth local bit line.
7. A semiconductor device according to claim 6 ,
wherein the first sense amplifier has a P-type MOSFET pair whose gates and drains are cross-coupled and whose sources are commonly coupled, and an N-type MOSFET pair whose gates and drains are cross-coupled and whose sources are commonly coupled, and
wherein the second sense amplifier has a P-type MOSFET pair whose gates and drains are cross-coupled and whose sources are commonly coupled, and an N-type MOSFET pair whose gates and drains are cross-coupled and whose sources are commonly coupled.
8. A semiconductor device according to claim 5 ,
wherein the first memory array further has a fourth bit line coupled to the first pre-amplifier,
wherein the second memory array further has a fifth bit line coupled to the second pre-amplifier and a sixth bit line coupled to the second pre-amplifier,
wherein the first pre-amplifier has a first MOSFET whose gate is coupled to the first bit line and whose source or drain is coupled to the first local bit line, and a second MOSFET whose gate is coupled to the fourth bit line and whose source or drain is coupled to the third local bit line,
wherein the second pre-amplifier has a third MOSFET whose gate is coupled to the second bit line and whose source or drain is coupled to the first local bit line, and a fourth MOSFET whose gate is coupled to the fifth bit line and whose source or drain is coupled to the third local bit line,
wherein the third pre-amplifier has a fifth MOSFET whose gate is coupled to the third bit line and whose source or drain is coupled to the second local bit line, and a sixth MOSFET whose gate is coupled to the sixth bit line and whose source or drain is coupled to the fourth local bit line.
9. A semiconductor device according to claim 1 ,
wherein each of the first to third memory cells has a capacitor and a transistor.