Method and mechanism to determine keeper size
View Patent ↗A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.
1. For a dynamic circuit comprising a pre-charge circuit, a pull down network (PDN), and a keeper transistor, all of which are coupled to a dynamic node of the dynamic circuit, a machine-implemented method for determining a size for the keeper transistor, comprising:
determining an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node, wherein determining the estimated amount of leakage current comprises:
performing a computer simulation on a partial circuit that includes the pre-charge circuit and the PDN but not the keeper transistor, wherein the computer simulation simulates behavior of the partial circuit when the PDN is not actively discharging the dynamic node; and
obtaining, from a set of simulation results, the estimated amount of leakage current that passes through the PDN; and
determining a size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current.
2. The method of claim 1 , further comprising:
after performing the step of determining the size of the keeper transistor, reducing the size of the keeper transistor based, at least in part, on an acceptable level of voltage loss at the dynamic node.
3. The method of claim 1 , further comprising:
accessing data that describes what size said keeper transistor would need to be to supply a specified amount of on current.
4. The method of claim 1 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a logic high voltage to the dynamic node.
5. The method of claim 1 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a voltage that is less than a logic high voltage to the dynamic node.
6. For a dynamic circuit comprising a pre-charge circuit, a pull down network (PDN), and a keeper transistor, all of which are coupled to a dynamic node of the dynamic circuit, a machine-readable storage medium carrying one or more sequences of instructions for determining a size for the keeper transistor, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:
determining an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node, wherein determining the estimated amount of leakage current comprises:
performing a computer simulation on a partial circuit that includes the pre-charge circuit and the PDN but not the keeper transistor, wherein the computer simulation simulates behavior of the partial circuit when the PDN is not actively discharging the dynamic node; and
obtaining, from a set of simulation results, the estimated amount of leakage current that passes through the PDN; and
determining a size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current.
7. The machine-readable storage medium of claim 6 , wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the step of:
after performing the step of determining the size of the keeper transistor, reducing the size of the keeper transistor based, at least in part, on an acceptable level of voltage loss at the dynamic node.
8. The machine-readable storage medium of claim 6 , wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to further perform the step of:
accessing data that describes what size said keeper transistor would need to be to supply a specified amount of on current.
9. The machine-readable storage medium of claim 6 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a logic high voltage to the dynamic node.
10. The machine-readable storage medium of claim 6 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a voltage that is less than a logic high voltage to the dynamic node.
11. For a dynamic circuit comprising a pre-charge circuit, a pull down network (PDN), and a keeper transistor, all of which are coupled to a dynamic node of the dynamic circuit, an apparatus for determining a size for the keeper transistor, comprising:
one or more processors; and
a machine-readable medium, coupled to the one or more processors, carrying one or more sequences of instructions for determining a size for the keeper transistor, wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to perform the steps of:
determining an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node, wherein determining the estimated amount of leakage current comprises:
performing a computer simulation on a partial circuit that includes the pre-charge circuit and the PDN but not the keeper transistor, wherein the computer simulation simulates behavior of the partial circuit when the PDN is not actively discharging the dynamic node; and
obtaining, from a set of simulation results, the estimated amount of leakage current that passes through the PDN; and
determining a size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current.
12. The apparatus of claim 11 , wherein execution of the one or more sequences of instructions by the one or more processors further causes the one or more processors to perform the step of:
after performing the step of determining the size of the keeper transistor, reducing the size of the keeper transistor based, at least in part, on an acceptable level of voltage loss at the dynamic node.
13. The apparatus of claim 11 , wherein execution of the one or more sequences of instructions by the one or more processors further causes the one or more processors to perform the step of:
accessing data that describes what size said keeper transistor would need to be to supply a specified amount of on current.
14. The apparatus of claim 11 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a logic high voltage to the dynamic node.
15. The apparatus of claim 11 , wherein the step of determining an estimated amount of leakage current comprises:
assigning a voltage that is less than a logic high voltage to the dynamic node.