Organic light emitting diode device capable of decreasing data procesing capacity and timing controller suitable for the same

1. An organic light emitting diode (OLED) device comprising:

a timing controller for performing a gamma correction of inputted image data for the OLED device, and then changing a bit number of the gamma-corrected image data to thereby output converted image data, wherein the inputted image data has 6 bits, the gamma-corrected image data has 8 bits; and

a data drive unit for outputting a data drive signal on the basis of the converted image data;

wherein the timing controller converts gamma characteristic of the inputted image data according to a gamma 2.2 curve when performing the gamma correction of the inputted image data;

wherein the timing controller converts gamma characteristic of the inputted image data by determining RGB image data corresponding to the inputted image data from a look-up table;

wherein the look-up table is formed in a method of mapping the RGB image data having the converted gamma characteristics by each gray level of the image data;

wherein the timing controller includes:

a data correction unit for correcting the inputted image data to have predetermined gamma characteristics; and

a data control unit for controlling high bit data of the gamma-corrected image data in frequency and location by time and space, according to the remaining low bit data of the gamma-corrected image data;

wherein the data of 8 bits of the gamma-corrected image data outputted from the data correction unit is divided into data of high 7 bits and data of low 1 bit;

wherein the high 7 bits is referring to 7 most significant bits within the 8 bit data, and the low 1 bit is referring to one least significant bit;

wherein four adjacent pixels display the data of the existing high 7 bits of the 8 bit data when the data of the low 1 bit of the 8 bit data is ‘0’;

wherein two pixels among the four adjacent pixels display the data of the existing high 7 bits of the 8 bit data while another two pixels among the four adjacent pixels display high 7-bit+1 which is obtained by adding the value of ‘1’ to the existing high 7 bit data of the 8 bit data when the data of the low 1 bit of the 8 bit data is ‘1’.

2. The OLED device of claim 1 , further comprising:

a gate drive unit for outputting a gate drive signal according to a control signal provided from the timing controller; and

an OLED panel being driven by the data drive unit and the gate drive unit.

3. The OLED device of claim 1 , wherein the data control unit is formed of a frame rate control (FRC) and dithering unit.

4. A timing controller suitable for an organic light emitting diode (OLED) device, the timing controller comprising:

a gamma correction unit to receive an n-bit data and convert the n-bit data to an m-bit data by a gamma correction process; and

a control unit to convert the m-bit data to an n′-bit data by a dithering process;

wherein the n-bit data has 8 bits and the m-bit data has 10 bits;

wherein the gamma correction unit converts gamma characteristic of the n-bit data according to a gamma 2.2 curve when converting the n-bit data to the m-bit data by the gamma correction process;

wherein the timing controller converts gamma characteristic of the inputted image data by determining RGB image data corresponding to the inputted image data from a look-up table;

wherein the look-up table is formed in a method of mapping the RGB image data having the converted gamma characteristics by each gray level of the image data;

wherein the timing controller includes:

a data correction unit for correcting the inputted image data to have predetermined gamma characteristics; and

a data control unit for controlling high bit data of the gamma-corrected image data in frequency and location by time and space, according to the remaining low bit data of the gamma-corrected image data;

wherein data of 10 bits from the data correction unit is divided into data of high 8 bits and data of low 2 bits;

wherein four adjacent pixels display the data of the existing high 8 bits of the 10-bit data while the low 2 bits of the 10-bit data are dropped when the data of the low 2 bits is ‘00’;

wherein one pixel among the four adjacent pixels displays 8 bit+1 data, which is obtained by adding a value of ‘1’ to the existing high 8-bit data of the 10-bit data and displaying the added resultant data of 8 bits when the data of the low 2 bits is ‘01’;

wherein two pixels among the four adjacent pixels display the data of high 8 bit+1 while the other two pixels among the four adjacent pixels display the data of the existing high 8 bits when the data of the low 2 bits is ‘10’;

wherein three pixels among the four adjacent pixels display the data of high 8 bit+1 while the remaining one pixel displays the data of the existing high 8 bits when the data of the low 2 bits is ‘11’.