IP Library › Granted Patent US 7,242,255

Granted Patent B1

US 7,242,255 · App. 11/120,914 · Granted Jul 10, 2007

Method and apparatus for minimizing phase error and jitter in a phase-locked loop

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Quick Facts

Patent No.: US 7,242,255
App. No.: 11/120,914
Granted: Jul 10, 2007
Kind: B1

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Abstract

An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.

Claims (65)

1. An apparatus that minimizes phase error and jitter in a phase-locked loop, comprising:

a phase/frequency detector;

a charge pump;

a loop filter;

a voltage-controlled oscillator; and

a frequency divider;

wherein the phase/frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator, and frequency divider are coupled together to form a phase-locked loop;

wherein the charge pump contains a pull-up network and a pull-down network which are coupled to each other, a current compensation device, a replica of the pull-up network and a replica of the pull-down network which are coupled to each other, and a replica of the current compensation device;

wherein the replica of the pull-up network and the replica of the pull-down network both conduct current continuously; and

wherein if the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through one of the pull-up network and through the pull-down network such that the current flowing through the pull-up network and through the pull-down network are substantially equal, so that substantially no current flows into a capacitor of the loop filter, thereby substantially minimizing a build-up of charge on the capacitor which can cause phase error and jitter in the phase-locked loop.

2. The apparatus of claim 1 ,

wherein the replica of the pull-up network, the replica of the pull-down network, and the replica of the current compensation device are coupled in a negative feedback loop;

wherein the negative feedback loop is referenced to the pull-up network, the pull-down network, and the current compensation device;

wherein the negative feedback loop determines a control voltage for the replica of the current compensation device;

wherein the control voltage for the replica of the current compensation device forces a current flowing through the replica of the pull-up network and through the replica of the pull-down network to be substantially equal;

wherein the control voltage for the replica of the current compensation device also controls the current compensation device for the pull-up network and the pull-down network;

wherein if the pull-up network and the pull-down network are both conducting, and the current compensation device is connected to the pull-down network, the control voltage for the replica of the current compensation device controls the current compensation device for the pull-down network so that the current flowing through the pull-up network and through the pull-down network are substantially equal; and

wherein if the pull-up network and the pull-down network are both conducting, and the current compensation device is connected to the pull-up network, the control voltage for the replica of the current compensation device controls the current compensation device for the pull-up network so that the current flowing through the pull-up network and through the pull-down network are substantially equal.

3. The apparatus of claim 1 ,

wherein the current flowing through the replica of the pull-up network, the replica of the pull-down network, and the replica of the current compensation device settles more quickly than the current through the pull-up network, the pull-down network, and the current compensation device.

4. The apparatus of claim 1 ,

wherein if the current compensation device is coupled to the pull-up network, the current compensation device adjusts current in the pull-up network to substantially match the current flowing through the pull-down network; and

wherein if the current compensation device is coupled to the pull-down network, the current compensation device adjusts current in the pull-down network to substantially match the current flowing through the pull-up network.

5. A computer system including a phase-locked loop that minimizes phase error and jitter, comprising:

a processor;

a memory; and

a phase-locked loop;

wherein the phase-locked loop is comprised of,

a phase/frequency detector,

a charge pump,

a loop filter,

a voltage-controlled oscillator, and

a frequency divider;

wherein the charge pump contains a pull-up network and a pull-down network which are coupled to each other, a current compensation device; a replica of the pull-up network and a replica of the pull-down network which are coupled to each other, and a replica of the current compensation device;

wherein the replica of the pull-up network and the replica of the pull-down network both conduct current continuously; and

6. The computer system of claim 5 ,

wherein the replica of the pull-up network, the replica of the pull-down network, and the replica of the current compensation device are coupled in a negative feedback loop;

wherein the negative feedback loop is referenced to the pull-up network, the pull-down network, and the current compensation device;

wherein the negative feedback loop determines a control voltage for the replica of the current compensation device;

wherein the control voltage for the replica of the current compensation device also controls the current compensation device for the pull-up network and the pull-down network; and

7. The computer system of claim 5 ,

8. The computer system of claim 5 ,

9. A method for minimizing phase error and jitter in a phase-locked loop which includes, a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, wherein the charge pump contains a pull-up network and a pull-down network which are coupled to each other, a current compensation device, a replica of the pull-up network and a replica of the pull-down network which are coupled to each other, and a replica of the current compensation device, wherein the replica of the pull-up network and the replica of the pull-down network both conduct current continuously, and the method comprising:

determining at the current compensation device if the pull-up network and the pull-down network are both conducting;

if so, adjusting currents flowing through one of the pull-up network and through the pull-down network such that the current flowing through the pull-up network and through the pull-down network are substantially equal, so that substantially no current flows into a capacitor of the loop filter, thereby substantially minimizing a build-up of charge on the capacitor which can cause phase error and jitter in the phase-locked loop.

10. The method of claim 9 , wherein adjusting the currents involves:

coupling the replica of the pull-up network, the replica of the pull-down network, and the replica of the current compensation device in a negative feedback loop;

referencing the negative feedback loop to the pull-up network, the pull-down network, and the current compensation device;

using the negative feedback loop to determine a control voltage for the replica of the current compensation device; and

using the control voltage for the replica of the current compensation device to force a current flowing through the replica of the pull-up network and through the replica of the pull-down network to be substantially equal; and

using the control voltage for the replica of the current compensation device to control the current compensation device for the pull-up network and the pull-down network;

11. The method of claim 9 ,

12. The method of claim 9 ,

wherein if the current compensation device is coupled to the pull-up network, the adjusting the currents involves adjusting current in the pull-up network to substantially match the current flowing through the pull-down network; and

wherein if the current compensation device is coupled to the pull-down network, the adjusting the currents involves adjusting current in the pull-down network to substantially match the current flowing through the pull-up network.

Assignments (2)

MERGER AND CHANGE OF NAME Recorded Dec 16, 2015

From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.

To: ORACLE AMERICA, INC.

Reel/Frame 037302/0772 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2005

From: CHEN, YEN-CHUNG T.; NAGARAKANTI, KAILASHNATH; OH, SUNG-HUN

To: SUN MICROSYSTEMS, INC.

Reel/Frame 016534/0199 →