Output buffer circuit and control method therefor

1. An output buffer circuit comprising:

first and second output transistors connected in series between a first power supply and a second power supply;

first and second control circuits, connected to the first and second output transistors, for receiving an input signal and respectively generating first and second control signals for controlling the first and second output transistors, wherein the first and second output transistors generate an output signal at an output terminal of the output buffer circuit; and

a third control circuit, connected between the output terminal and the first and second control circuits, for receiving the input signal and the output signal and controlling a slew rate of the output signal by controlling slew rates of the first and second control signals in accordance with the input signal and the output signal, wherein the third control circuit controls the first and second control circuits when the first and second output transistors are turned off to generate the first and second control signal in accordance with the input signal, and controls the first and second control circuits when the first and second output transistors are turned on such that the first and second control signals sharply rise or fall in response to a change in the input signal, gently rise or fall after a predetermined time elapses, and thereafter sharply rise or fall when the output signal reaches a predetermined level.

2. The output buffer circuit according to claim 1 , wherein the first and second control circuits respectively include first and second switching elements and first and second resistor elements respectively connected in parallel to the first and second switching elements; and

the output buffer circuit further comprises a delay circuit, connected to the third control circuit, for generating a delay signal by delaying the input signal,

wherein when the first and second output transistors are turned on, the third control circuit controls the first and second control circuits in accordance with the delay signal and the output signal such that the first and second control signals are generated by turning on and off the first and second switching elements.

3. The output buffer circuit according to claim 2 , wherein the third control circuit includes:

a first inverter circuit, connected to the output terminal and having a relatively low threshold voltage, for receiving the output signal and generating a first inverted signal;

a second inverter circuit, connected to the output terminal and having a relatively high threshold voltage, for receiving the output signal and generating a second inverted signal;

a NAND gate, connected to the delay circuit and the first inverter circuit, for receiving the delay signal and the first inverted signal and generating a first switching control signal for controlling the first switching element; and

a NOR gate, connected to the delay circuit and the second inverter circuit, for receiving the delay signal and the second inverted signal and generating a second switching control signal for controlling the second switching element.

4. The output buffer circuit according to claim 2 , wherein the third control circuit includes:

a Schmitt inverter circuit, connected to the output terminal and having a hysteresis characteristic, for receiving the output signal and generating an inverted output signal;

a NAND gate, connected to the delay circuit and the Schmitt inverter circuit, for receiving the delay signal and the inverted output signal and generating a first switching control signal for controlling the first switching element; and

a NOR gate, connected to the delay circuit and the Schmitt inverter circuit, for receiving the delay signal and the inverted output signal and generating a second switching control signal for controlling the second switching element.

5. An output buffer circuit comprising:

first and second output transistors connected in series between a first power supply and a second power supply;

first and second control circuits, respectively connected to the first and second output transistors, for receiving an input signal and respectively generating first and second control signals for controlling the first and second output transistors, wherein the first and second output transistors generate an output signal that is output from an output terminal of the output buffer circuit in response to the first and second control signals, the first and second control circuits respectively including first and second switching elements and first and second resistor elements respectively connected in parallel to the first and second switching elements; and

a third control circuit, connected between the output terminal and the first and second control circuits, for receiving the input signal and the output signal and controlling a slew rate of the output signal by controlling slew rates of the first and second control signals in accordance with the input signal and the output signal, the third control circuit including,

a first inverter circuit, connected to the output terminal and having a relatively low threshold voltage, for receiving the output signal and generating a first inverted signal,

a second inverter circuit, connected to the output terminal and having a relatively high threshold voltage, for receiving the output signal and generating a second inverted signal,

a NAND gate, connected to the first inverter circuit, for receiving the input signal and the first inverted signal and generating a first switching control signal for controlling the first switching element, and

a NOR gate, connected to the second inverter circuit, for receiving the input signal and the second inverted signal and generating a second switching control signal for controlling the second switching element.

6. An output buffer circuit comprising:

first and second output transistors connected in series between a first power supply and a second power supply;

first and second control circuits, respectively connected to the first and second output transistors, for receiving an input signal and respectively generating first and second control signals for controlling the first and second output transistors, wherein the first and second output transistors generate an output signal that is output from an output terminal of the output buffer circuit in response to the first and second control signals, the first and second control circuits respectively including first and second switching elements and first and second resistor elements respectively connected in parallel to the first and second switching elements; and

a third control circuit, connected between the output terminal and the first and second control circuits, for receiving the input signal and the output signal and controlling a slew rate of the output signal by controlling slew rates of the first and second control signals in accordance with the input signal and the output signal, the third control circuit including,

a Schmitt inverter circuit, connected to the output terminal and having a hysteresis characteristic, for receiving the output signal and generating an inverted output signal,

a NAND gate, connected to the Schmitt inverter circuit, for receiving the input signal and the inverted output signal and generating a first switching control signal for controlling the first switching element, and

a NOR gate, connected to the Schmitt inverter circuit, for receiving the input signal and the inverted output signal and generating a second switching control signal for controlling the second switching element.

7. A semiconductor device comprising:

an output buffer circuit including,

first and second output transistors connected in series between a first power supply and a second power supply,

first and second control circuits, connected to the first and second output transistors, for receiving an input signal and respectively generating first and second control signals for controlling the first and second output transistors, wherein the first and second output transistors generate an output signal output from an output terminal of the output buffer circuit in response to the first and second control signals, and

a third control circuit, respectively connected between the output terminal and the first and second control circuits, for receiving the input signal and the output signal and controlling a slew rate of the output signal by controlling slew rates of the first and second control signals in accordance with the input signal and the output signal, wherein the third control circuit controls the first and second control circuits when the first and second output transistors are turned off to generate the first and second control signal in accordance with the input signal, and controls the first and second control circuits when the first and second output transistors are turned on such that the first and second control signals sharply rise or fall in response to a change in the input signal, gently rise or fall after a predetermined time elapses, and thereafter sharply rise or fall when the output signal reaches a predetermined level.