Insulated gate transistor
View Patent ↗An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type disposed in contact with the semiconductor thin film. A gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.
1. An insulated gate transistor comprising:
a semiconductor thin film having a first main surface and a second main surface;
a first gate insulating film formed on the first main surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film;
a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film, a gate threshold voltage of the first conductive gate being controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions;
a third gate insulating film formed on a portion of the second main surface of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region, an end of the third semiconductor region being disposed within a distance in which carriers of the second conductivity type diffuse from the portion of the second main surface of the semiconductor thin film; and
a third conductive gate disposed in contact with the third gate insulating film.
2. An insulated gate transistor according to claim 1 ; further comprising an insulating substrate supporting the semiconductor thin film.
3. An insulated gate transistor according to claim 1 ; further comprising a substrate supporting the semiconductor thin film, the substrate having a portion forming the second conductive gate.
4. An insulated gate transistor according to claim 1 ; further comprising a substrate supporting at least an end of the semiconductor thin film.
5. An insulated gate transistor according to claim 1 ; wherein the first conductive gate is formed of silicon of the second conductivity type.
6. An insulated gate transistor according to claim 1 ; wherein the third conductive gate is formed of silicon of the second conductivity type.
7. An insulated gate transistor according to claim 1 ; wherein the first conductive gate is formed of silicon germanium of the second conductivity type.
8. An insulated gate transistor according to claim 1 ; wherein the first conductive gate is formed from p-type silicon germanium containing 45% to 60% of germanium in average; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
9. An insulated gate transistor according to claim 1 ; wherein the first conductive gate is formed from a laminate of a p-type silicon germanium layer containing 45% to 60% of germanium in average and a silicon layer; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
10. An insulated gate transistor according to claim 1 ; wherein a portion having a higher impurity concentration than the portion of the semiconductor thin film disposed the first semiconductor region and the second semiconductor region is formed in an extended portion of the semiconductor thin film leading to the third semiconductor region.
11. An insulated gate transistor according to claim 1 ; wherein the semiconductor thin film is doped with an impurity of the second conductivity type; and wherein an extended portion of the semiconductor thin film is doped with an impurity of the first conductivity type.
12. An insulated gate transistor comprising:
a semiconductor thin film having a first main surface and a second main surface;
a first gate insulating film formed on the first main surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film;
a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film;
a third gate insulating film formed on a portion of the second main surface of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region, an end of the third semiconductor region being disposed within a distance in which carriers of the second conductivity type diffuse from the portion of the second main surface of the semiconductor thin film, and a gate threshold voltage of the first conductive gate being controlled by injection of the carriers into the semiconductor thin film from the third semiconductor region; and
a third conductive gate disposed in contact with the third gate insulating film.
13. An insulated gate transistor according to claim 12 ; further comprising an insulating substrate supporting the semiconductor thin film.
14. An insulated gate transistor according to claim 12 ; further comprising a substrate supporting the semiconductor thin film, the substrate having a portion forming the second conductive gate.
15. An insulated gate transistor according to claim 12 ; further comprising a substrate supporting at least an end of the semiconductor thin film.
16. An insulated gate transistor according to claim 12 ; wherein the first conductive gate is formed of silicon of the second conductivity type.
17. An insulated gate transistor according to claim 12 ; wherein the third conductive gate is formed of silicon of the second conductivity type.
18. An insulated gate transistor according to claim 12 ; wherein the first conductive gate is formed of silicon germanium of the second conductivity type.
19. An insulated gate transistor according to claim 12 ; wherein the first conductive gate is formed from p-type silicon germanium containing 45% to 60% of germanium in average; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
20. An insulated gate transistor according to claim 12 ; wherein the first conductive gate is formed from a laminate of a p-type silicon germanium layer containing 45% to 60% of germanium in average and a silicon layer; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
21. An insulated gate transistor according to claim 12 ; wherein a portion having a higher impurity concentration than the portion of the semiconductor thin film disposed the first semiconductor region and the second semiconductor region is formed in an extended portion of the semiconductor thin film leading to the third semiconductor region.
22. An insulated gate transistor according to claim 12 ; wherein the semiconductor thin film is doped with an impurity of the second conductivity type; and wherein an extended portion of the semiconductor thin film is doped with an impurity of the first conductivity type.
23. An insulated gate transistor comprising:
a semiconductor thin film having a first main surface and a second main surface;
a first gate insulating film formed on the first main surface of the semiconductor thin film;
a first conductive gate formed on the first gate insulating film;
first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film;
a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film;
a third gate insulating film formed on a portion of the second main surface of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region; and
a third conductive gate disposed in contact with the third gate insulating film, the third conductive gate partially overlapping the third semiconductor region with the third gate insulating film being disposed therebetween so that a gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.
24. An insulated gate transistor according to claim 23 ; further comprising an insulating substrate supporting the semiconductor thin film.
25. An insulated gate transistor according to claim 23 ; further comprising a substrate supporting the semiconductor thin film, the substrate having a portion forming the second conductive gate.
26. An insulated gate transistor according to claim 23 ; further comprising a substrate supporting at least an end of the semiconductor thin film.
27. An insulated gate transistor according to claim 23 ; wherein the first conductive gate is formed of silicon of the second conductivity type.
28. An insulated gate transistor according to claim 23 ; wherein the third conductive gate is formed of silicon of the second conductivity type.
29. An insulated gate transistor according to claim 23 ; wherein the first conductive gate is formed of silicon germanium of the second conductivity type.
30. An insulated gate transistor according to claim 23 ; wherein the first conductive gate is formed from p-type silicon germanium containing 45% to 60% of germanium in average; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
31. An insulated gate transistor according to claim 23 ; wherein the first conductive gate is formed from a laminate of a p-type silicon germanium layer containing 45% to 60% of germanium in average and a silicon layer; and wherein the portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region contains an n-type impurity in a dose of 1.2×10 12 to 1.6×10 12 atoms/cm 2 .
32. An insulated gate transistor according to claim 23 ; wherein a portion having a higher impurity concentration than the portion of the semiconductor thin film disposed the first semiconductor region and the second semiconductor region is formed in an extended portion of the semiconductor thin film leading to the third semiconductor region.
33. An insulated gate transistor according to claim 23 ; wherein the semiconductor thin film is doped with an impurity of the second conductivity type; and wherein an extended portion of the semiconductor thin film is doped with an impurity of the first conductivity type.