Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device
View Patent ↗A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and a semiconductor region of a second conductive type arranged on the substrate, and a highly-doped buried layer of the second conductive type and a highly-doped bottom layer of the first conductive type are arranged between the substrate and the semiconductor region, and the first highly-doped bottom layer of the first conductive type is arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extends by a predetermined distance to the second region, and a first isolation region is arranged on the highly-doped bottom layer extending from the first region in the second region, and a highly-doped region of the second conductive type is arranged on the highly-doped buried layer, and a second isolation region is arranged on a second highly-doped bottom layer of the first conductive type. By such structure, parasitic bipolar junction transistors in the first isolation region and the second isolation region can be electrically separated from the third region.
1. A power semiconductor device having a first region in which a transistor is formed, a third region in which a control element is formed, and a second region arranged horizontally between the first region and the third region to electrically separate the transistor from the control element, the device comprising:
a substrate of the first conductive type;
a semiconductor region of the second conductive type arranged on the substrate;
a highly-doped buried layer of a second conductive type arranged in the first region and the third region between the substrate and the semiconductor regions, the highly-doped buried layer of the second conductive type extending by a predetermined distance from the first region in the second region;
a highly-doped bottom layer of a first conductive type comprising a first highly-doped bottom layer of the first conductive type arranged on a top side and a bottom side of the highly-doped buried layer in the first region and extending by a predetermined distance from the first region in the second region, and a second highly-doped bottom layer of the first conductive type separated by a predetermined distance from the highly-doped buried layer in the second region;
an isolation region, comprising a first isolation region having a top surface and a bottom surface, the bottom surface arranged to contact an upper portion of the first highly-doped bottom layer of a first conductive type, and a second isolation region arranged to contact an upper portion of the second highly-doped bottom layer of the first conductive type, the isolation region formed in the semiconductor region of the second region; and
a highly-doped region of a second conductive type having a top surface and a bottom surface, the bottom surface arranged to contact an upper portion of the highly-doped buried layer of the second conductive type between the first isolation region and the second isolation region, the highly-doped region of the second conductive type formed in the semiconductor region of the second region;
wherein the first isolation region and the highly-doped region of a second conductive type each have an electrical contact terminal at their corresponding top surfaces, formed in the region of the top surfaces closest to the second insulation region.
2. The power semiconductor device according to claim 1 , wherein the highly-doped buried layer of the second conductive type is longer than the highly-doped bottom layer of the first conductive type in the second region.
3. The power semiconductor device according to claim 1 , wherein a DMOS (double diffused MOS) transistor is arranged on the first highly-doped bottom layer of the first conductive type in the first region.
4. The power semiconductor device according to claim 3 , wherein the DM 0 S transistor comprises:
a well region of the second conductive type arranged on the first highly-doped bottom layer of a first conductive type;
a body region of the first conductive type formed on an upper surface of the well region;
a drain region separated by a predetermined distance from the body region on an upper surface of the well region;
a source region arranged in the body region;
a gate insulating layer arranged on a channel forming region of the body region; and
a gate conductive layer arranged on the gate insulating layer.
5. The power semiconductor device according to claim 1 , wherein the impurity density in the highly-doped bottom layer of the second conductive type extending from the first region to the second region is in a range of 1×10 19 /cm 3 to 9×10 19 /cm 3 .
6. The power semiconductor device according to claim 1 , wherein the first conductive type is p type, and the second conductive type is n type.
7. The power semiconductor device of claim 1 , wherein no parasitic transistor is connected to both the first region and the third region.