IP Library Granted Patent US 7,329,551
Granted Patent B2
US 7,329,551 · App. 11/124,439 · Granted Feb 12, 2008

Manufacturing and testing of electrostatic discharge protection circuits

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,329,551
App. No.
11/124,439
Granted
Feb 12, 2008
Kind
B2
Abstract

A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Claims (28)

1. A method for manufacturing a semiconductor device, comprising:

fabricating a die comprising a device having a first bonding pad and ESD protection circuitry having a second bonding pad;

testing the device using a test system electrically connected to the first bonding pad; and

after testing, connecting the first bonding pad to the second bonding pad, wherein the ESD protection circuitry becomes functional to protect the device against electrostatic discharge after connecting the first bonding pad to the second bonding pad.

2. The method of claim 1 , wherein the device comprises a power MOSFET, and the die comprises a gate pad that is connected to a gate of the power MOSFET in the die.

3. The method of claim 2 , wherein testing the device comprises applying to the gate of the power MOSFET a voltage that is higher than the ESD protection circuitry permits when the ESD protection circuitry is functional.

4. The method of claim 2 , wherein the first bonding pad is the gate pad of the power MOSFET.

5. The method of claim 2 , wherein the first bonding pad is a source pad that is connected to a source of the power MOSFET.

6. The method of claim 1 , wherein before connecting the first bonding pad to the second bonding pad, the method further comprises testing the ESD protection circuitry using a test system that is electrically connected to the second bonding pad.

7. The method of claim 1 , wherein testing is performed while the die is part of a wafer containing multiple dice.

8. The method of claim 7 , wherein connecting the first bonding pad to the second bonding pad is performed after the die is separated from the wafer.

9. The method of claim 1 , wherein connecting the first bonding pad to the second bonding pad is performed during packaging of the die.

10. The method of claim 1 , wherein connecting the first bonding pad to the second bonding pad comprises forming a wire bond that contacts the first bonding pad and the second bonding pad.

11. The method of claim 1 , wherein connecting the first bonding pad to the second bonding pad comprises:

connecting a first wire to the first bonding pad and to a portion of a lead frame; and

connecting a second wire to the second bonding pad and to the portion of the lead frame.

12. The method of claim 11 , wherein the portion of the lead frame includes an external lead that provides an electrical connection to the first and second bonding pads in a package containing the die.

13. The method of claim 1 , wherein connecting the first bonding pad to the second bonding pad comprises:

forming a first conductive bump on the first bonding pad;

forming a second conductive bump on the second bonding pad; and

connecting the first conductive bump and the second conductive bump to a conductive region.

14. The method of claim 13 , wherein connecting the first and second conductive bumps to a conductive region comprises:

bringing a face of the die on which the first and second conductive bumps were formed into contact with a substrate including the conductive region; and

performing a reflow process that attaches the conductive bumps to the conductive region.

15. A method for manufacturing a semiconductor device, comprising:

fabricating a die comprising a device having a first bonding pad and ESD protection circuitry having a second bonding pad;

testing the ESD protection circuitry using a test system electrically connected to the second bonding pad; and

after testing, connecting the first bonding pad to the second bonding pad, wherein the ESD protection circuitry becomes functional to protect the device against electrostatic discharge after connecting the first bonding pad to the second bonding pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2025
From: ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 071234/0320 →