Field effect transistor and method of fabricating the same
View Patent ↗Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
1. A method of fabricating a field effect transistor, comprising:
forming a doped poly silicon pattern on a substrate;
forming a first insulating layer spacer on a sidewall of the poly silicon pattern;
forming a source junction in the substrate beneath both the poly silicon pattern and the first insulating layer spacer by diffusing impurity ions doped in the poly silicon pattern;
forming a gate insulating layer on an entire surface of the structure;
forming a conductive layer spacer on the gate insulating layer at a sidewall of the first insulating layer spacer;
forming a second insulating layer spacer on a sidewall of the conductive layer spacer;
forming a third insulating layer spacer on a sidewall of the second insulating layer spacer;
forming a drain extending region beneath the third insulating layer spacer and in an exposed region of the substrate;
forming a gate electrode formed of the conductive layer spacer, a source layer formed of the poly silicon pattern, and a drain layer formed of the poly silicon layer after forming and planarizing the doped poly silicon layer on an entire surface of the structure; and
forming a drain junction in the substrate by diffusing impurity ions doped in the drain layer downward.
2. The method according to claim 1 , wherein the first insulating layer spacer and the third insulating layer spacer are formed of oxide layers, and the second insulating layer spacer is formed of a high dielectric insulating layer.
3. The method according to claim 2 , wherein the high dielectric insulating layer is formed of one selected from a group consisting of Al 2 O 3 , ZrSi x O y , HfSi x O y , HfAl x O y , LaSi x O y , ZrAl x O y , ZrN x O y , ZrO 2 , HfO 2 , La 2 O 3 , Pr 2 O 3 , Ta 2 O 5 , and a compound thereof.
4. The method according to claim 1 , wherein the drain extending region is formed by an ion implantation process.
5. The method according to claim 1 , wherein the drain junction is formed to be thinner than the source junction.
6. The method according to claim 1 , wherein the impurity ions are diffused by an annealing process.