Semiconductor memory device
View Patent ↗Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.
1. A semiconductor memory device, comprising:
a plurality of non-volatile memory circuits in one chip, each of the non-volatile memory circuits executing a data erase operation in response to receiving a control signal to execute the data erase operation, and after the data erase operation has completed, outputting a local completion signal distinct from the control signal;
a continuous erase control circuit outputting a continuous erase start signal in response to an inputted continuous erase command; and
a shift circuit outputting the control signal to a first one of the plurality of non-volatile memory circuits and receiving from the first one of the plurality of non-volatile memory circuits the local completion signal, and then outputting the control signal to the rest of the plurality of non-volatile memory circuits sequentially upon receiving the local completion signal from the preceding non-volatile memory circuit, and outputting a continuous erase completion signal upon receiving the local completion signal from the last of the plurality of non-volatile memory circuits, based on the continuous erase start signal outputted from the continuous erase control circuit.
2. The semiconductor memory device according to claim 1 , wherein the shift circuit comprises a plurality of holding circuits connected in cascade, each of which is respectively disposed in association with one of the non-volatile memory circuits, and
the holding circuit outputs the control signal to a corresponding non-volatile memory circuit, and supplies the signal indicative of completion of the data erase operation from the corresponding non-volatile memory circuit to the holding circuit connected to the succeeding stage.
3. The semiconductor memory device according to claim 2 , wherein the holding circuit comprises:
a flip-flop which outputs the control signal; and
a logical operation circuit to which the control signal and the signal indicative of completion of the data erase operation from the corresponding non-volatile memory circuit are inputted, and whose output is supplied to a flip-flop of the holding circuit connected to the succeeding stage.
4. The semiconductor memory device according to claim 1 , wherein the control signal is a signal to control as to whether the non-volatile memory circuit is put into operation or not.
5. The semiconductor memory device according to claim 1 , wherein the control signal is a signal for effecting control of oscillation of an operation clock signal generated in the non-volatile memory circuits.
6. The semiconductor memory device according to claim 1 , further comprising:
an interface circuit receiving an inputted command,
wherein the interface circuit gives, to the continuous erase control circuit, instructions for outputting the continuous erase start signal based on the inputted continuous erase command, and stops the operation of the continuous erase control circuit based on the continuous erase completion signal from the shift circuit.
7. The semiconductor memory device according to claim 1 , wherein each of the non-volatile memory circuits is comprised of a memory cell section relating to storing data and a peripheral circuit for reading relating to an operation of data reading from the memory cell section.
8. The semiconductor memory device according to claim 7 , wherein the peripheral circuit for reading is disposed near the memory cell section.
9. The semiconductor memory device according to claim 7 , wherein a peripheral circuit other than the memory cell section and the peripheral circuit for reading in each of the non-volatile memory circuit is disposed as a common circuit which is used in common by the plurality of non-volatile memory circuits.
10. The semiconductor memory device according to claim 9 , wherein the common circuit includes at least one of a peripheral circuit for rewriting relating to data rewriting operation and a peripheral circuit for erasing relating to data erase operation for the memory cell sections.
11. The semiconductor memory device according to claim 7 , wherein the memory cell section and the peripheral circuit for reading, comprising:
a memory cell array having a plurality of bit lines and a plurality of word lines, and having memory cells for storing data are disposed at each of the interconnections of the bit lines and the word lines respectively;
a bit line decoder selecting a bit line;
a word line decoder selecting a word line;
a voltage generating circuit generating a voltage supplying to the word lines in the case to read data from the memory cells; and
a sense amplifier circuit amplifying data read from the memory cells.
12. The semiconductor memory device according to claim 7 , wherein a signal path for executing data rewriting in the memory cell section and a signal path for executing data reading from the memory cell section are able to be separated in the non-volatile memory circuits.
13. The semiconductor memory device according to claim 7 , wherein a signal path for executing data rewriting in the memory cell section and a signal path for executing data reading from the memory cell section are connected via a switching circuit.