IP Library Granted Patent US 7,890,071
Granted Patent B2
US 7,890,071 · App. 11/126,554 · Granted Feb 15, 2011

Handheld audio system

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Quick Facts
Patent No.
US 7,890,071
App. No.
11/126,554
Granted
Feb 15, 2011
Kind
B2
Abstract

A handheld audio system includes a radio signal decoder integrated circuit (IC) and a digital audio processing integrated circuit. The radio signal decoder integrated circuit produces a digital left channel signal and a digital right channel signal from a received radio signal in accordance with an enable signal and also produces a system clock. The digital audio processing integrated circuit includes a DC-to-DC converter and a processing module. The DC-to-DC converter is operably coupled to produce at least one power supply voltage based on the system clock. The processing module is operably coupled to produce the enable signal when the at least one power supply voltage has reached a desired level and to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.

Claims (50)

1. A handheld audio system, comprising:

a radio signal decoder integrated circuit that produces:

a digital left channel signal and a digital right channel signal from a received radio signal in accordance with a first enable signal; and

a system clock in response to a second enable signal, the second enable signal generated when a first power supply voltage from a DC-to-DC converter of a digital audio processing integrated circuit reaches a desired level; and

the digital audio processing integrated circuit, wherein the digital audio processing integrated circuit is a different integrated circuit than the radio signal decoder integrated circuit and is coupled to the radio signal decoder integrated circuit, and wherein the digital audio processing integrated circuit comprises:

the DC-to-DC converter to produce at least one power supply voltage that includes the first power supply voltage, wherein the at least one power supply voltage is based on the system clock when the DC-to-DC converter receives output of the system clock from the radio signal decoder integrated circuit; and

a processing module to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.

2. The handheld audio system of claim 1 , wherein the at least one power supply voltage includes an integrated circuit process dependent supply voltage and an input/output dependent supply voltage.

3. The handheld audio system of claim 1 , further comprising:

a crystal oscillator circuit operably coupled to the radio signal decoder integrated circuit, wherein the radio signal decoder integrated circuit produces the system clock from a reference oscillation produced by the crystal oscillator circuit.

4. The handheld audio system of claim 1 , further comprising:

an antenna structure to provide the received radio signal to the radio signal decoder integrated circuit.

5. The handheld audio system of claim 1 , wherein the processing module generates the second enable signal when the first power supply voltage reaches the desired level.

6. The handheld audio system of claim 1 , further comprising:

a bidirectional interface to couple the radio signal decoder integrated circuit to the digital audio processing integrated circuit.

7. The handheld audio system of claim 1 , wherein the radio signal decoder integrated circuit includes a power enable module to generate the second enable signal when the at least one power supply voltage reaches the desired level.

8. The system of claim 1 , wherein the at least one power supply voltage is based on an internal oscillation before the DC-to-DC converter receives output of the system clock from the radio signal decoder integrated circuit.

9. A method, comprising:

producing a digital left channel signal and a digital right channel signal with a radio signal decoder integrated circuit from a received radio signal in accordance with an enable signal;

producing a system clock with the radio signal decoder integrated circuit, wherein the system clock is used to generate a system clock signal comprising a plurality of clocking periods and a plurality of quiet periods, wherein the digital left channel signal and the digital right channel signal are transmitted serially to a digital audio processing integrated circuit during the clocking periods and are not transmitted to the digital audio processing integrated circuit during the quiet periods;

producing at least one power supply voltage based on the system clock or an internal oscillation with a DC-to-DC converter of a digital audio processing integrated circuit; and

producing audio signals for audio playback with a processing module of the digital audio processing integrated circuit, wherein the audio signals are produced from at least one of the digital left and right channel signals and a stored digital audio file.

10. The method of claim 8 , further comprising:

producing a reference oscillation with a crystal oscillator circuit operably coupled to the radio signal decoder integrated circuit; and

producing the system clock from the reference oscillation.

11. The method of claim 9 , further comprising:

producing a reference oscillation with a crystal oscillator circuit operably coupled to the radio signal decoder integrated circuit, wherein the system clock is produced based on the reference oscillation.

12. The method of claim 9 , further comprising:

providing the received radio signal to the radio signal decoder integrated circuit via an antenna structure operably coupled to the radio signal decoder integrated circuit.

13. The method of claim 9 , further comprising:

generating the enable signal with the processing module when the at least one power supply voltage reaches a desired level.

14. The method of claim 9 , further comprising:

coupling the radio signal decoder integrated circuit to the digital audio processing integrated circuit with a bidirectional interface.

15. The method of claim 9 , further comprising:

generating the enable signal with a power enable module of the radio signal decoder integrated circuit when the at least one power supply voltage reaches a desired level.

16. The method of claim 9 , further comprising initially producing the digital left channel signal and the digital right channel signal when the radio signal decoder integrated circuit begins producing the system clock.

17. A system, comprising:

a radio signal decoder integrated circuit that produces:

a digital left channel signal and a digital right channel signal from a received radio signal in accordance with an enable signal; and

a system clock, wherein the system clock generates a system clock signal comprising a plurality of clocking periods and a plurality of quiet periods, wherein the digital left channel signal and the digital right channel signal are transmitted serially during the clocking periods and are not transmitted during the quiet periods; and

a digital audio processing integrated circuit coupled to the radio signal decoder integrated circuit, wherein the digital audio processing integrated circuit comprises:

a DC-to-DC converter to produce at least one power supply voltage based on the system clock or an internal oscillation; and

a processing module to receive the system clock, to receive a serial transmission of the digital left and right channel signals, and to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.

18. A method, comprising:

producing a first power supply voltage with a DC-to-DC converter of a digital audio processing integrated circuit, the first power supply voltage based on an internal oscillation;

producing system clock output with a radio signal decoder integrated circuit in response to an enable signal, wherein the radio signal decoder integrated circuit is separate from the digital audio processing integrated circuit;

changing the first power supply voltage produced by the DC-to-DC converter to a second power supply voltage, the second power supply voltage based on the system clock output when the DC-to-DC converter receives the system clock output; and

sending a digital left channel signal and a digital right channel signal to the digital audio processing integrated circuit from the radio signal decoder integrated circuit based on the system clock output, wherein the digital left channel signal and the digital right channel signal are produced by the radio signal decoder integrated circuit from received radio signals.

19. The method of claim 18 , further comprising sending the enable signal to the radio signal decoder integrated circuit from a processing module of the digital audio processing integrated circuit when the first power supply voltage based on the internal oscillation reaches a desired value.

20. The method of claim 18 , further comprising generating the enable signal with a power enable module of the radio signal decoder integrated circuit when the first power supply voltage based on the internal oscillation reaches a desired value.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: SIGMATEL, LLC
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037583/0428 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
CHANGE OF NAME Recorded Nov 23, 2015
From: SIGMATEL INC.
To: SIGMATEL, LLC
Reel/Frame 037152/0127 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →