IP Library Patent Application 11127133
Patent Application
App. No. 11/127,133

System LSI and data processing system

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Quick Facts
Patent No.
US None
App. No.
11/127,133
Abstract

The system LSI has a MCU, a memory access control means equipped with unified memory interfaces with which at least two lines of unified memories A and B can be connected. In the main unit of the data processing system, the purpose of each unified memory is set like “mainly for main storage” or “mainly for display” by software in accordance with the operating status of the data processing system so as to adjust the memory access performance. In addition, the system has a means for specifying the unified memory to access and area therein for every display plane to be controlled by the display control circuit.

Claims (44)

1 . A system LSI comprising

a command processing section,

a display control section, and

a memory access control means which at least two physically different storage devices can be connected with and controls the access to the storage devices;

the storage area of the storage devices being capable of having an area to be accessed by the command processing section and an area to be accessed by the display control section; and

the area to be accessed by the command processing section for main storage purpose and the area to be accessed by the display control section for display purpose being utilized separately based on the purpose of the access to the at-least two storage devices via the memory access control means.

2 . A system LSI according to claim 1 , wherein

the method of memory access employed is such that the access to the at-least two storage devices can be specified using address.

3 . A system LSI according to claim 1 , wherein

the method of memory access employed is such that the access to the at-least two storage devices can be specified using register.

4 . A data processing system comprising a system LSI according to claim 1 , at least two physically different storage devices connected with the system LSI, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the display control section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

5 . A system LSI according to claim 1 , wherein the display control section has a function of controlling multiple image planes, and

has a means for specifying which storage device to access for each of the image planes.

6 . A data processing system comprising a system LSI according to claim 5 , at least two physically different storage devices connected with the system LSI, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the display control section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

7 . A system LSI according to claim 5 , wherein the function of controlling multiple image planes is a function of superposing the multiple image planes as a display plane, and which area of the storage device to access is specified for each of the image planes.

8 . A data processing system comprising a system LSI according to claim 7 , at least two physically different storage devices connected with the system LSI, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the display control section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

9 . A system LSI according to claim 7 , wherein the display control section has a register for specifying where to access for each of the image planes, and makes an access for each of the image planes in accordance with the setting in the register.

10 . A data processing system comprising a system LSI according to claim 9 , at least two physically different storage devices connected with the system LSI, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the display control section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

11 . A system LSI comprising

a command processing section,

an image input section, and

a memory access control means which at least two physically different storage devices can be connected with and controls the access to the storage devices;

the storage area of the storage devices being capable of having an area to be accessed by the command processing section and an area to be accessed by the image input section; and

the area to be accessed by the command processing section for main storage purpose and the area to be accessed by the image input section for image input purpose being utilized separately based on the purpose of the access to the at-least two storage devices via the memory access control means.

12 . A system LSI according to claim 11 , wherein the method of memory access employed is such that the access to the at-least two storage devices can be specified using register.

13 . A system LSI according to claim 11 , wherein the method of memory access employed is such that the access to the at-least two storage devices can be specified using address.

14 . A data processing system comprising a system LSI according to claim 11 , at least two physically different storage devices connected therewith, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the image input section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

15 . A system LSI comprising

a command processing section,

a voice processing section, and

a memory access control means which at least two physically different storage devices can be connected with and controls the access to the storage devices;

the storage area of the storage devices being capable of having an area to be accessed by the command processing section and an area to be accessed by the voice processing section; and

the area to be accessed by the command processing section for main storage purpose and the area to be accessed by the voice processing section for voice processing purpose being utilized separately based on the purpose of the access to the at-least two storage devices via the memory access control means.

16 . A system LSI according to claim 15 , wherein

the method of memory access employed is such that the access to the at-least two storage devices can be specified using address.

17 . A system LSI according to claim 15 , wherein

the method of memory access employed is such that the access to the at-least two storage devices can be specified using register.

18 . A data processing system comprising a system LSI according to claim 15 , at least two physically different storage devices connected therewith, and external devices;

the system LSI utilizing separately the area to be accessed by the command processing section and the area to be accessed by the voice processing section based on the purpose of the access to the at-least two storage devices, including the access by the external devices, and in accordance with the operating status of the system.

Assignments (3)
CHANGE OF NAME Recorded Aug 27, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024900/0594 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2005
From: TAKAHASHI, YOSHITAKA; MATSUMOTO, YOSHIYUKI; NARUSE, TAKANOBU; SAITO, SEIICHI; NAKATSUKA, YASUHIRO
To: RENESAS TECHNOLOGY CORPORATION
Reel/Frame 017003/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2005
From: TAKAHASHI, YOSHITAKA; MATSUMOTO, YOSHIYUKI; NARUSE, TAKANOBU; SAITO, SEIICHI; NAKATSUKA, YASUHIRO
To: RENESAS TECHNOLOGY CORPORATION
Reel/Frame 016563/0386 →