Piezoresistive sensing structure

1. A method for manufacturing a piezoresistive sensing structure comprising a beam, said method comprising the steps of:

implanting a piezoresistive element into a first side of an assembly, wherein the assembly includes a semiconductor material having a beam region corresponding to a desired pattern for the beam and adjacent areas to the beam region;

forming a passivation layer on the first side of the assembly over the element;

removing the passivation layer from the adjacent areas on the first side of the assembly such that said passivation layer overlies the beam region and has an edge at the adjacent areas and a border adjacent to the edge;

providing a first mask on the passivation layer in a desired pattern, said mask having a sidewall overlying the passivation layer such that the border is exposed between the edge of the passivation layer and the sidewall; and

etching to remove the adjacent areas of the assembly, and thereby form the beam in the assembly over at least a portion of the assembly that is to provide a cavity, wherein the passivation layer provides a second mask in the formation of the beam that determines a width of the formed beam, and wherein the beam includes the element.

2. The method of claim 1 , wherein the assembly includes a first wafer having the cavity formed into a first side of the first wafer and a second wafer having a first side and a second side opposite the first side, wherein the second side of the second wafer is bonded to the first side of the first wafer.

3. The method of claim 2 , wherein the second wafer is an N-type epitaxial wafer.

4. The method of claim 3 , wherein the element is a P-type piezoresistive element.

5. The method of claim 2 , wherein the width of the beam substantially corresponds to a width of the passivation layer that is formed on an area of the first side of the second wafer that is to become the beam.

6. The method of claim 5 , wherein the width of the beam is about 15 microns.

7. The method of claim 2 , wherein the passivation layer includes a thermal oxide layer and a silicon nitride layer.

8. The method of claim 2 , wherein the beam is formed with a deep reactive ion etch (DRIE).

9. A method for manufacturing a piezoresistive sensing structure comprising a beam, said method comprising the steps of:

providing an assembly including a first wafer having a cavity formed into a first side of the first wafer and a second wafer having a first side and a second side opposite the first side, wherein the second side of the second wafer is bonded to the first side of the first wafer;

implanting a plurality of piezoresistive elements into the first side of the second wafer, wherein said first side of second wafer has beam regions corresponding to the desired patterns for the beams and adjacent areas to the beam regions;

forming a passivation layer on the first side of the second wafer;

removing the passivation layer from the adjacent areas on the first side of the second wafer such that said passivation layer overlies the beam regions and has an edge at the adjacent areas and a border adjacent to the edge;

providing a first mask on the passivation layer in a desired pattern said mask having a sidewall overlying the passivation layer such that the border is exposed between the edge of the passivation layer and the sidewall; and

eching to remove the adjacent areas of the second wafer, and thereby form the central mass that is coupled to a peripheral frame with a plurality of beams in the second wafer, wherein the passivation layer provides a second mask in the formation of the beams that determines a width of the formed beams, and wherein each of the beams includes one of the elements.

10. The method of claim 9 , wherein the second wafer is an epitaxial wafer.

11. The method of claim 10 , wherein the epitaxial wafer is an N-type epitaxial wafer.

12. The method of claim 9 , wherein the elements are P-type piezoresistive elements.

13. The method of claim 9 , wherein the width of the beams substantially corresponds to a width of the passivation layer that is formed on an area of the first side of the second wafer that is to become the beams.

14. The method of claim 9 , wherein the passivation layer includes a thermal oxide layer and a silicon nitride layer.

15. The method of claim 9 , wherein the central mass and the beams are formed with a deep reactive ion etch (DRIE).