Method and apparatus for buffering bi-directional open drain signal lines
View Patent ↗A buffer system includes a logic adjusting circuit for translating a first logic level of a first component to a second logic level of a second component. The first and second logic level values are substantially different, and the buffer system has no directional control signal. A method of interfacing at least two components with different logic voltage requirements on a single bus without a separate directional control signal includes initializing a buffering circuit, activating the buffering circuit, transferring data through the buffering circuit, and deactivating the buffering circuit. A method of implementing a bi-directional interface between at least two devices interfaced on a bus includes providing a plurality of logic components interconnected to transfer data through the bus, and transferring data through the bus from a first device to a second device. The direction of data transfer is determined without a separate directional control signal.
1. A buffering apparatus, comprising:
a first interface for receiving/transmitting a first input/output from/to a first component having a first predetermined set of logic voltage levels;
a second interface for receiving/transmitting a second input/output from/to a second component having a first predetermined set of logic voltage levels;
a buffering system disposed between the first and second interfaces, the buffering system being clocked by a clock signal and comprising first and second synchronization paths connected to the first and second interfaces, respectively, and first and second sets of cross-coupled NOR gates connected to the first and second interfaces, respectively, wherein each of the first and second synchronization paths comprises a plurality of flip-flops connected in series and clocked by the clock signal, and wherein a number of flip-flops in the first and second synchronization paths is determined by a ratio of a frequency of the clock signal to a frequency of transitions between logic voltage levels at the first interface or second interface.
2. The apparatus as claimed in claim 1 , wherein the buffering system includes a first and a second input/output circuit, and a voltage adjusting circuit.
3. The apparatus as claimed in claim 1 , wherein the first and second interfaces comprise first and second pull-up resistors, respectively.
4. The apparatus as claimed in claim 1 , wherein each of the first and second interfaces comprises an input/output circuit that includes an input buffer, a tri-state output buffer, and a bonding pad, and wherein the input/output circuits of the first and second interfaces are configured as mirror images of each other.
5. A circuit arrangement, comprising:
a first input/output circuit, the first input/output circuit including a first I/O pad with a first bonding pad, a first input buffer, and a first output buffer;
a first delay circuit, the first delay circuit including a first set of at least two flip-flops and a first set of cross-coupled NOR gates;
a second delay circuit, the second delay circuit including a second set of at least two flip-flops and a second set of cross-coupled NOR gates; and
a second input/output circuit, the second input/output circuit including a second I/O pad with a second bonding pad, a second input buffer, and a second output buffer.
6. The apparatus of claim 3 , wherein each of the first and second pull-up resistors has a rinse time, and wherein the number of flip-flops in the first and second synchronization paths further depends on the rise time of the first and second pull-up resistors.
7. The apparatus of claim 6 , wherein the number of flip-flops in the first synchronization path depends on the rise time of the second pull-up resistor and the number of flip-flops in the second synchronization path depends on the rise time of the first pull-up resistor.
8. The apparatus of claim 6 , wherein a ratio of the frequency of the clock signal to a frequency of logic level transitions and accordingly the number of flip-flops in the first and second synchronization paths determines an ability to match a slowest time of the first and second pull-up resistors.
9. A bi-directional buffer device, comprising:
a first input/output circuit for connection to a first component having a first set of logic voltage levels;
a second input/output circuit for connection to a second component having a second set of logic levels;
wherein the first input/output circuit and the second input/output circuit comprise components that are connected in mirror image configurations of each other;
a buffer circuit connected between the first input/output circuit and the second input/output circuit, wherein the buffer circuit comprises a first delay circuit comprising a first set of at least two flip-flops and a set of cross-coupled NOR gates and a second delay circuit comprising a second set of at least two flip-flops and a set of cross-coupled NOR gates.
10. The device of claim 9 , wherein the flip-flops in the first and second delay circuit are clocked by a clock signal, and wherein a number of flip-flops in the first and first delay circuit and in second delay circuits is determined by a ratio of a frequency of the clock signal to a frequency of transitions between logic voltage levels at the first or second input/output circuit.
11. The device of claim 10 , and further comprising a first pull-up resistor connected to the first input/output circuit and a second pull-up resistor connected to the second input/output circuit.
12. The device of claim 11 , wherein each of the first and second pull-up resistors has a rise time, and wherein the number of flip-flops in the first and second delay circuits further depends on the rise time of the first and second pull-up resistors.
13. The device of claim 12 , wherein the number of flip-flops in the first delay circuit depends on the rise time of the second pull-up resistor and the number of flip-flops in the second delay circuit depends on the rise time of the first pull-up resistor.