Semiconductor device having multiple lateral channels and method of forming the same
View Patent ↗A semiconductor device having multiple lateral channels with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a first lateral channel above the conductive substrate and a second lateral channel above the first lateral channel. The semiconductor device further includes a second contact above the second lateral channel. The semiconductor device still further includes an interconnect that connects the first and second lateral channels to the conductive substrate operable to provide a low resistance coupling between the first contact and the first and second lateral channels.
1. A semiconductor device, comprising:
a substrate having a source contact covering a substantial portion of a bottom surface thereof;
a first buffer layer formed over said substrate;
an isolation layer formed over said first buffer layer;
a first spacer layer formed over said isolation layer;
a second buffer layer formed over said first spacer layer;
a first barrier layer formed over said second buffer layer;
a second spacer layer formed over said first barrier layer;
a first lateral channel formed over said second spacer layer;
a third spacer layer formed over said first lateral channel;
a fourth spacer layer formed over said third spacer layer;
a second lateral channel formed over said fourth spacer layer;
a fifth spacer layer formed over said second lateral channel;
a sixth spacer layer formed over said fifth spacer layer;
a third lateral channel formed over said sixth spacer layer;
a seventh spacer layer formed over said third lateral channel;
a second barrier layer formed over said seventh spacer layer;
a recess layer formed over said second barrier layer;
an etch-stop layer formed over said recess layer;
first and second source/drain contact layers formed over said etch-stop layer;
a source interconnect that connects said first, second and third lateral channels to said substrate operable to provide a low resistance coupling between said source contact and said first, second and third lateral channels;
a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer;
a dielectric layer formed over said gate, and said first and second source/drain contact layers;
a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers; and
a drain contact coupled to said drain post.
2. The semiconductor device as recited in claim 1 wherein said substrate is formed from gallium arsenide.
3. The semiconductor device as recited in claim 1 wherein said isolation layer forms an intrinsic body diode at least in part with said first barrier layer.
4. The semiconductor device as recited in claim 1 wherein said second buffer layer is an alternating aluminum-gallium arsenide/gallium arsenide (“AlGaAs/GaAs”) super-lattice buffer.
5. The semiconductor device as recited in claim 1 wherein said first barrier layer is formed from aluminum gallium-arsenide (“AlGaAs”).
6. The semiconductor device as recited in claim 1 wherein said first barrier layer is modulation doped.
7. The semiconductor device as recited in claim 1 wherein said isolation layer forms back-to-back diodes at least in part with said first buffer layer and said first barrier layer.
8. The semiconductor device as recited in claim 1 wherein said first, second and third lateral channels are formed from indium gallium arsenide.
9. The semiconductor device as recited in claim 1 wherein said first, second and third lateral channels are pseudomorphic.
10. The semiconductor device as recited in claim 1 wherein said third, fifth and seventh spacer layers are modulation doped.
11. The semiconductor device as recited in claim 1 wherein said source interconnect is located in a source via formed through said semiconductor device down to said substrate.
12. The semiconductor device as recited in claim 1 wherein said source interconnect has a metal layer on horizontal and semi-horizontal surfaces thereof.
13. The semiconductor device as recited in claim 1 wherein said source interconnect is plated with a metal material.
14. The semiconductor device as recited in claim 1 wherein said gate is formed by multiple layers.
15. The semiconductor device as recited in claim 1 wherein said drain post is plated with a metal material.
16. The semiconductor device as recited in claim 1 wherein said source and drain contacts are formed by a metallic alloy.
17. The semiconductor device as recited in claim 1 wherein said semiconductor device is a depletion mode device.
18. The semiconductor device as recited in claim 1 wherein said semiconductor device is an enhancement mode device.
19. The semiconductor device as recited in claim 1 wherein said seventh spacer layer is modulation doped to a selected level to provide an enhancement mode device.
20. The semiconductor device as recited in claim 1 wherein said gate recess is further recessed into said semiconductor device proximate said third lateral channel thereby providing an enhancement mode device.