Thin film transistor with common contact hole and fabrication method thereof
View Patent ↗The present invention provides a TFT substrate that includes a plurality of TFTs each of which have a gate, a source and a drain. The plurality of the TFTs may be formed by first and second active regions formed on the substrate that each have a source region that corresponds to a source and a drain region that corresponds to a drain. An offset region may be formed between the first and second active regions. A single contact hole may reach both the offset region and the adjacent source/drain regions of the first and second active regions.
1. A thin film transistor substrate including a plurality of thin film transistors each transistor having a gate, a source, and a drain, the thin film transistor substrate comprising:
a substrate;
a first active region and second active region formed on the substrate and respectively having a source/drain region;
an undoped offset region formed only between the first active region and the second active region; and
a contact hole exposing the offset region and adjacent source/drain regions of the first active region and the second active region.
2. The thin film transistor substrate of claim 1 , wherein the offset region is formed between the adjacent source/drain regions of the first active region and the second active region.
3. The thin film transistor substrate of claim 1 , wherein the offset region has a dimension of at least 0.5 μm in length.
4. The thin film transistor substrate of claim 1 , wherein the offset region is a polysilicon layer comprised of an amorphous silicon layer crystallized after dehydrogenation.
5. A thin film transistor substrate including a plurality of thin film transistors each having a gate, a source, and a drain, the thin film transistor substrate comprising:
a substrate; a first active region formed by doping a first impurity to a polysilicon layer on the substrate so as to include source/drain regions;
a second active region formed by doping a second impurity to the polysilicon layer on the substrate so as to include source/drain regions;
an undoped offset region formed only between the first active region and the second active region;
a gate insulating layer formed over the first active region and the second active region;
a first gate electrode and a second gate electrode respectively formed, on the gate insulating layer, above the first active region and the second active region; and
a single contact hole exposing the offset region and adjacent source/drain regions of the first active region and the second active region.
6. The thin film transistor substrate of claim 5 , wherein the offset region is formed between the adjacent source/drain regions of the first active region and the second active region.
7. The thin film transistor substrate of claim 5 , wherein one of the first and second impurities is a P-type impurity when the other is an N-type impurity.
8. The thin film transistor substrate of claim 5 , wherein the source/drain regions comprises a lightly doped drain region.
9. The thin film transistor substrate of claim 5 , wherein the polysilicon layer comprises an amorphous silicon layer crystallized by excimer laser annealing after dehydrogenation.
10. A method for fabricating a thin film transistor substrate, comprising:
forming a first active region and a second active region on a substrate, each of the first active region and the second active region including source/drain regions;
doping the source/drain regions of the first active region and the second active region with different types of impurities;
forming an undoped offset region only between adjacent source/drain regions of the first active region and the second active region;
forming a single contact hole exposing the offset region and the adjacent source/drain regions of the first active region and the second active region; and
coupling the adjacent source/drain regions of the first active region and the second active region through the single contact hole.
11. The method as claimed in claim 10 , wherein one of the first and second active regions is a PMOS region and the other is an NMOS region.
12. The method as claimed in claim 10 , wherein the doping of the source/drain regions comprises:
forming a gate insulating layer on the first active region and the second active region;
doping different high-concentration impurities to the first active region and the second active region; and
doping different low-concentration impurities to the first active region and the second active region so as to form lightly doped drain regions.
13. The method as claimed in claim 10 , wherein forming the offset region includes masking the offset region during the doping of the source/drain regions.
14. The method as claimed in claim 10 , wherein the offset region has a dimension of at least about 0.5 μm in length.
15. The method as claimed in claim 10 , wherein a conductive material fills the contact hole so as to couple the adjacent source/drain regions.
16. A flat panel display comprising a display panel, a scan driver for applying selections signals to the display panel, and a data driver for applying data signals to the display panel, wherein at least one of the display panel, the scan driver, and the data driver comprises:
a substrate;
a first active region and a second active region formed on the substrate, each of the first active region and the second active region having a source/drain region;
an undoped offset region formed only between the first active region and the second active region; and
a contact hole exposing the offset region and adjacent source/drain regions of the first active region and the second active region.
17. The flat panel display of claim 16 , wherein the offset region is formed between the adjacent source/drain regions of the first active region and the second active region.
18. The flat panel display of claim 16 , wherein one of the first and second active regions is a PMOS region and the other is an NMOS region.