Gate driver output stage with bias circuit for high and wide operating voltage range
View Patent ↗A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.
1. An output stage for a drive circuit comprising:
first and second semiconductor devices each having a respective pair of main terminals, one main terminal of each of said devices being connected in series to form a half-bridge, an output drive signal being supplied at said connection point, each device further having a respective control terminal, said control terminals being connected together to receive a control signal;
a third semiconductor device having one main terminal which receives a supply voltage, another main terminal connected in series with said first device, and a control terminal for receiving a bias voltage, said third device providing a voltage drop according to said bias voltage to prevent said supply voltage from being fully applied to said first and second devices;
wherein said first, second and third devices are integrated in a semiconductor chip; and
wherein said first and second devices are formed in a low-side well and said third device is formed in a high-side well of said chip.
2. An output stage for a drive circuit according to claim 1 , wherein said devices are formed in an epitaxial layer of a first conductivity type which is formed on a substrate also of said first conductivity type.
3. An output stage for a drive circuit according to claim 1 , wherein said first and second devices are of complementary conductivity types, and said first and third devices are of complementary conductivity types.
4. An output stage for a drive circuit according to claim 1 , wherein said first and second devices are of the same conductivity type.
5. An output stage for a drive circuit according to claim 4 , wherein said third device is also of said same conductivity type.
6. An output stage for a drive circuit according to claim 1 , further comprising a bias circuit integrated in said semiconductor chip, comprising:
a fourth semiconductor device having a first main terminal which receives said supply voltage and a second main terminal which supplies said bias voltage to said control terminal of said third device;
a voltage divider connected at one end to said third device control terminal and at another end to a common point;
an error amplifier having a positive input receiving an output of said voltage divider and a negative input receiving a reference voltage referenced to said common point;
said error amplifier having an output driving a control terminal of a fifth semiconductor device, one main terminal of said fifth device being connected to a control terminal of said fourth device, the other main terminal of said fifth device being connected to said common point; and
a resistance connected between said supply voltage input and the control terminal of said fourth device.
7. An output stage for a drive circuit according to claim 6 , wherein said bias circuit generates a bias voltage determined by the equation:
V
BIAS
=
R
2
R
1
+
R
2
·
V
REF
wherein V REF is said reference voltage, and R 1 and R 2 are two resistances of said voltage divider.
8. An output stage for a drive circuit according to claim 6 , wherein the other main terminal of said second semiconductor device is connected directly to said common point.
9. An output stage for a drive circuit according to claim 1 , wherein said second and third devices are of the same conductivity type.
10. An output stage for a drive circuit according to claim 1 , wherein said first and second devices have a predetermined safe voltage, and said voltage drop reduces said supply voltage so that said first and second devices receive no more than said predetermined safe voltage.
11. An output stage for a drive circuit according to claim 1 , wherein said bias voltage is referenced to a common point, and the other main terminal of said second semiconductor device is connected directly to said common point.