Granted Patent B2

US 7,262,585 · App. 11/130,675 · Granted Aug 28, 2007

Abstract

Claims (50)

1. A power supply system comprises:

a transistor having an input, a substrate, a first node, and a second node, the first node operably coupled to a non-battery power source;

a linear regulator operably coupled to the second node to produce a regulated output voltage based on the non-battery power source, when enabled;

a DC-DC converter operably coupled to produce the regulated output voltage based on a battery power source, when enabled; and a control circuit operably coupled to the input node and the substrate of the transistor wherein when the DC-DC converter is enabled, the control circuit controls a reverse leakage current of the transistor, and when the linear regulator is enabled in a zero load-state, the control circuit controls a forward leakage current of the transistor, and when the linear regulator is enabled in a non-zero load-state, the control circuit provides a current limit for the linear regulator.

2. The power supply system of claim 1 wherein the control circuit comprises:

an impedance operably coupled to the substrate and to the first node of the transistor to control the reverse leakage current across the transistor.

3. The power supply system of claim 2 wherein the control circuit further comprises

a current limit module operably coupled to the input of the transistor, wherein the current limit module provides, in the zero load-state, a first voltage less than the threshold voltage of the transistor, the current limit module provides, in the non-zero load-state, a second voltage greater than the threshold voltage of the transistor, but less than a saturation voltage of the transistor, to provide a first level of current limiting of the transistor.

4. The power supply system of claim 3 wherein the current limit module further functions to:

provide a third voltage that is greater than the threshold voltage but less than the saturation voltage to the input of the transistor when in a second non-zero load-state to provide a second level of current limiting of the transistor.

5. The power supply system of claim 3 wherein the current limit module further functions to:

provide a third voltage that is greater than the saturation voltage to the input of the transistor when in a second zero load-state to provide a second level of current limiting of the transistor.

6. The power supply system of claim 3 wherein the current limit module comprises at least one of:

a pull-up transistor operably coupled to the input of the transistor; and

a pull-down transistor operably coupled to the input of the transistor.

7. A linear regulator circuit with a bi-directional current limit comprises:

a transistor having an input, a substrate, a first node, and a second node, the first node operably coupled to a power source;

a linear regulator operably coupled to the second node to produce a regulated output voltage based on the power source, when enabled; and

a control circuit operably coupled to the input node and the substrate of the transistor wherein when the linear regulator is disabled, the control circuit controls a reverse leakage current across the transistor, and when the linear regulator is enabled in a zero load-state, the control circuit controls a forward leakage current across the transistor, and when the linear regulator is enabled in a non-zero load-state, the control circuit provides current limit for the linear regulator.

8. The linear regulator circuit of claim 7 wherein the control circuit comprises:

an impedance operably coupled to the substrate and to the first node of the transistor to control the reverse leakage current across the transistor.

9. The linear regulator circuit of claim 8 wherein the control circuit further comprises

a current limit module operably coupled to the input of the transistor, wherein the current limit module provides, in the zero load-state, a first voltage less than the threshold voltage of the transistor, the current limit module provides, in the first non-zero load-state, a second voltage greater than the threshold voltage of the transistor, but less than a saturation voltage of the transistor, to provide a first level of current limiting of the transistor.

10. The linear regulator circuit of claim 9 wherein the current limit module further functions to:

provide a third voltage that is greater than the threshold voltage but less than the saturation voltage to the input of the transistor when in the non-zero load-state to provide a second level of current limiting of the transistor.

11. The linear regulator circuit of claim 9 wherein the current limit module further functions to:

provide a third voltage that is greater than the saturation voltage to the input of the transistor when in a non-zero load-state to provide the second level of current limiting of the transistor.

12. The linear regulator circuit of claim 9 wherein the current limit module comprises at least one of:

a pull-up transistor operably coupled to the input of the transistor; and

a pull-down transistor operably coupled to the input of the transistor.

13. A multi-media system on a chip comprising:

a processing module;

a memory;

an input/output module; and

a power system module, operably coupled to provide a regulated supply voltage to the processing module, the memory, and the input/output module, wherein the power system module includes:

a transistor having an input, a substrate, a first node, and a second node, the first node operably coupled to a non-battery power source;

a linear regulator operably coupled to the second node to produce a regulated output voltage based on the non-battery power source, when enabled;

a DC-DC converter operably coupled to produce the regulated output voltage based on a battery power source, when enabled; and

a control circuit operably coupled to the input node and the substrate of the transistor wherein when the DC-DC converter is enabled, the control circuit controls a reverse leakage current across the transistor, and when the linear regulator is enabled in a zero load-state, the control circuit controls a forward leakage current across the transistor, and when the linear regulator is enabled in a non-zero load-state, the control circuit provides current limit for the linear regulator.

14. The multi-media system on a chip of claim 13 wherein the control circuit comprises:

an impedance operably coupled to the substrate and the input of the transistor to control the reverse leakage current of the transistor.

15. The multi-media system on a chip of claim 14 wherein the control circuit further comprises

a current limit module operably coupled to the input of the transistor, wherein the current limit module provides, in the zero load-state, a first voltage substantially equal to the threshold voltage of the transistor, the current limit module provides, in the non-zero load-state, a second voltage greater than the threshold voltage of the transistor, but less than a saturation voltage of the transistor, to provide a first level of current limiting of the transistor.

16. The multi-media system on a chip of claim 15 wherein the current limit module further functions to:

provide a third voltage that is greater than the threshold voltage but less than the saturation voltage to the input of the transistor when in the non-zero load-state to provide a second level of current limiting of the transistor.

17. The multi-media system on a chip of claim 15 wherein the current limit module further functions to:

provide a third voltage that is greater than the saturation voltage to the input of the transistor when in the non-zero load-state to provide a second level of current limiting of the transistor.

18. The multi-media system on a chip of claim 15 wherein the current limit module comprises at least one of:

a pull-up transistor operably coupled to the input of the transistor; and

a pull-down transistor operably coupled to the input of the transistor.

Assignments (12)