Shared bit line cross-point memory array manufacturing method
View Patent ↗A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross-point is formed between the bottom word line and the bit line and a second cross-point is formed between the bit line and the top word line. A resistive memory material is provided at each cross-point above and below the bit line. A diode is formed at each cross-point between the resistive memory material and either the top word line or the bottom word line, respectively.
1. A method of manufacturing a memory structure comprising:
a) providing a resistive cross-point memory array structure having a plurality of bit lines;
b) depositing a layer of resistive memory material overlying the plurality of bit lines;
c) forming an array of diode/metal electrode stacks overlying the layer of resistive memory material positioned above the plurality of bit lines, where the diode/metal electrode stacks are n+ polysilicon/p+ polysilicon/metal electrode stacks; and
d) patterning a plurality of top electrodes overlying the electrode stack to form a plurality of cross-points with the plurality of bit lines.
2. The method of claim 1 , further comprising depositing an insulating material overlying the plurality of bit lines and planarizing the insulating material to expose the plurality of bit lines prior to depositing the layer of resistive memory material, whereby bit lines are isolated from each other by the insulating material.
3. The method of claim 1 , wherein forming an array of diode/metal electrode stacks further comprises depositing a metal layer overlying the resistive memory material; depositing a polysilicon layer overlying the metal layer; patterning the polysilicon layer and the metal layer to form polysilicon/metal electrode stacks; isolating the polysilicon/metal electrode stacks; doping the polysilicon with a dopant, and doping the polysilicon with a counter dopant, whereby the polysilicon forms a diode.
4. The method of claim 3 , further comprising depositing a barrier layer overlying the metal layer prior to depositing the polysilicon layer.
5. The method of claim 3 , wherein the dopant is boron, and the counter dopant is phosphorous.
6. The method of claim 5 , wherein doping the polysilicon with boron comprises implanting boron ions at an energy of between approximately 100 keV and 200 keV and a dose of between approximately 1×10 14 /cm 2 and 1×10 15 /cm 2 .
7. The method of claim 5 , wherein doping the polysilicon with phosphorous comprises implanting phosphorous ions at an energy of between approximately 60 keV and 150 keV and a dose of between approximately 5×10 14 /cm 2 and 5×10 15 /cm 2 .
8. A method of manufacturing a memory structure comprising:
a) providing a resistive cross-point memory array structure having a plurality of bit lines;
b) depositing a layer of resistive memory material overlying the plurality of bit lines;
c) forming an array of diode/metal electrode stacks overlying the layer of resistive memory material positioned above the plurality of bit lines, where the diode/metal electrode stacks are p+ polysilicon/n+ polysilicon/metal electrode stacks; and
d) patterning a plurality of top electrodes overlying the electrode stack to form a plurality of cross-points with the plurality of bit lines.