IP Library Granted Patent US 7,352,163
Granted Patent B2
US 7,352,163 · App. 11/132,172 · Granted Apr 1, 2008

Early effect cancelling circuit, differential amplifier, linear regulator, and early effect canceling method

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Quick Facts
Patent No.
US 7,352,163
App. No.
11/132,172
Granted
Apr 1, 2008
Kind
B2
Abstract

In an input transistor of current mirror circuit, it is intended to prevent the current generated by Early effects from appearing in the output current of the current mirror circuit. Having an Early voltage detector 22 of same connection and structure as a driver circuit 21 , and connected in parallel to the driver circuit 21 , the current flowing in input transistor Q 9 of the Early voltage detector 22 is detected. Output current (current IQ 11 ) of Early voltage detector 22 is added to input current (current IQ 5 ) of driver circuit 21 . As a result, in input current (current IQ 7 ) of current mirror circuit 25 , current α due to Early voltage effects can be canceled. At the same time, current α due to Early voltage effects generated in input transistor Q 5 of current mirror circuit 25 is prevented from appearing in output current (current IQ 8 ) of current mirror circuit 25.

Claims (30)

1. An Early effect canceling circuit comprising:

a current mirror circuit;

a first input transistor for supplying input current to the current mirror circuit;

an auxiliary current mirror circuit for supplying a canceling current to the current mirror circuit, the auxiliary current mirror circuit having an output terminal that is connected to an input terminal of the current mirror circuit; and

a second input transistor for supplying the canceling current to the auxiliary current mirror circuit.

2. The Early effect canceling circuit of claim 1 , wherein the voltage applied to current route terminals of the first input transistor by way of the current mirror circuit is equivalent to the voltage applied to current route terminals of the second input transistor by way of the auxiliary current mirror circuit.

3. The Early effect canceling circuit of claim 1 , wherein the input current supplied from the first input transistor and the canceling current supplied from the second input transistor are different current values.

4. The Early effect canceling circuit of claim 1 , wherein the canceling current is supplied so as to decrease the input current supplied to the current mirror circuit.

5. The Early effect canceling circuit of claim 1 , wherein one current route terminal of the first input transistor is connected to a input terminal in the current mirror circuit to which a transistor connected as diode is connected, and one current route terminal of the second input transistor is connected to a control terminal of a transistor connected as diode in the auxiliary current mirror circuit.

6. The Early effect canceling circuit of claim 1 , wherein the current mirror circuit and first input transistor, and the auxiliary current mirror circuit and second input transistor are composed in same connection relation between terminals, respectively.

7. The Early effect canceling circuit of claim 1 , wherein the input current is a differential input current, and the differential current in the differential input current is calculated and issued.

8. The Early effect canceling circuit of claim 7 , wherein the canceling current is a current generated on the basis of either one of differential input currents.

9. The Early effect canceling circuit of claim 7 , further comprising:

a third input transistor connected to a output terminal in the current mirror circuit to which a transistor is not connected as diode,

wherein one of the differential input currents is fed into the first input transistor, and other differential input current is fed into the second input transistor and third input transistor.

10. The Early effect canceling circuit of claim 9 , wherein the canceling current supplied from the second input transistor, and the differential input current fed from the third input transistor are equal to each other, and the current supply capacity of the first input transistor is 2 times of the current supply capacity of the second input transistor and third input transistor.

11. The Early effect canceling circuit of claim 7 , further comprising a differential amplifier, wherein the differential input current is issued from the differential amplifier.

12. A differential amplifier having at least one transistor connected as diode as an active load element, and differential output terminals, comprising:

at least one auxiliary differential amplifier including a current mirror circuit as an active load element,

wherein a pair of input terminals in the auxiliary differential amplifier are connected to the differential input terminals, and the output terminal of the auxiliary differential amplifier is connected at least to either one of the differential output terminals.

13. The differential amplifier of claim 12 , further comprising:

two sets of the auxiliary differential amplifier, wherein the output terminal of each auxiliary differential amplifier is connected to each differential output terminal.

14. A control circuit of a DC-DC converter comprising:

an Early effect canceling circuit of claim 1 , wherein a main transistor is controlled depending on the output current of the Early effect canceling circuit.

15. A control circuit of a DC-DC converter comprising:

a differential amplifier of claim 12 , wherein a main transistor is controlled depending on an output current of the differential amplifier.

16. An Early effect canceling method comprising:

a step of supplying an input current containing a current generated by Early voltage effects to a current mirror circuit;

a step of supplying a canceling current containing a current generated by Early voltage effects to the current mirror circuit; and

a step of supplying a current obtained by subtracting the canceling current from the input current to the current mirror circuit.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 052487/0808 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2005
From: KIZAKI, YOSHIHIRO; YASUKOUCHI, KATSUYUKI; ITO, HIDENOBU
To: FUJITSU LIMITED
Reel/Frame 016588/0306 →